Patents by Inventor Mathieu Roy

Mathieu Roy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070072040
    Abstract: A fuel battery cell covered with a hydrophilic polymer layer.
    Type: Application
    Filed: September 28, 2006
    Publication date: March 29, 2007
    Applicant: STMicroelectronics S.A.
    Inventors: Sebastien Kouassi, Mathieu Roy
  • Publication number: 20060141339
    Abstract: A thin wafer comprising through holes filled at least partially with conductive carbon nanotubes generally oriented transversally to the wafer. A fuel cell comprising, in a thin wafer, a through hole filled with an electrolyte surrounded with barriers of carbon nanotubes generally oriented transversally to the wafer.
    Type: Application
    Filed: December 22, 2005
    Publication date: June 29, 2006
    Applicant: STMicroelectronics S.A.
    Inventors: Mathieu Roy, Fabien Pierre
  • Patent number: 6831338
    Abstract: A power component formed in an N-type silicon substrate delimited by a P-type wall, having a lower surface including a first P-type region connected to the wall, and an upper surface including a second P-type region, a conductive layer extending above the substrate between the second region and the wall. The component includes a third N-type region of high doping level formed in the substrate under the portion of the layer substantially halfway between the external periphery of the second region and the internal periphery of the wall. This third region is contacted by a field plate extending on either side of the third region in the direction of the wall and of the third region.
    Type: Grant
    Filed: October 19, 1999
    Date of Patent: December 14, 2004
    Assignee: STMicroelectronics S.A.
    Inventor: Mathieu Roy
  • Patent number: 6784465
    Abstract: A method for manufacturing a vertical power component on a substrate formed of a lightly-doped silicon wafer, including the steps of boring on the lower surface side of the substrate a succession of holes perpendicular to this surface; diffusing a dopant from the holes, of a second conductivity type opposite to that of the substrate; and boring similar holes on the upper surface side of the substrate to define an isolating wall and diffuse from these holes a dopant of the second conductivity type with a high doping level, the holes corresponding to the isolating wall being sufficiently close for the diffused areas to join laterally and vertically.
    Type: Grant
    Filed: April 25, 2003
    Date of Patent: August 31, 2004
    Assignee: STMicroelectronics S.A.
    Inventor: Mathieu Roy
  • Publication number: 20030219964
    Abstract: A method for manufacturing a vertical power component on a substrate formed of a lightly-doped silicon wafer, including the steps of boring on the lower surface side of the substrate a succession of holes perpendicular to this surface; diffusing a dopant from the holes, of a second conductivity type opposite to that of the substrate; and boring similar holes on the upper surface side of the substrate to define an isolating wall and diffuse from these holes a dopant of the second conductivity type with a high doping level, the holes corresponding to the isolating wall being sufficiently close for the diffused areas to join laterally and vertically.
    Type: Application
    Filed: April 25, 2003
    Publication date: November 27, 2003
    Applicant: STMicroelectronics S.A.
    Inventor: Mathieu Roy
  • Patent number: 6611006
    Abstract: A power component formed in an N-type silicon substrate, the lower and upper surfaces of which respectively include a first and a second P-type region that do not extend to the component periphery, a high voltage being capable of existing between the first and second regions and having to be withstood by the junctions between the first and second regions and the substrate. A deep insulating region that does not join the first region is provided at the lower periphery of the component, the lower surface of the substrate between said deep insulating region and the first region being coated with an insulating layer, the height of the deep insulating region being greater than that of a possible soldering upward extension formed during the soldering of the lower surface on a heat sink.
    Type: Grant
    Filed: May 15, 2001
    Date of Patent: August 26, 2003
    Assignee: STMicroelectronics S.A.
    Inventor: Mathieu Roy
  • Patent number: 6583487
    Abstract: A power component formed in an N-type silicon substrate delimited by a P-type wall, having a lower surface including a first P-type region connected to the wall, and an upper surface including a second P-type region, a conductive track extending above the substrate between the second region and the wall. The component includes a succession of trenches extending in the substrate under the track and perpendicularly to this track, each trench being filled with an insulator.
    Type: Grant
    Filed: October 19, 1999
    Date of Patent: June 24, 2003
    Assignee: STMicroelectronics S.A.
    Inventor: Mathieu Roy
  • Patent number: 6579782
    Abstract: A method for manufacturing a vertical power component on a substrate formed of a lightly-doped silicon wafer, including the steps of boring on the lower surface side of the substrate a succession of holes perpendicular to this surface; diffusing a dopant from the holes, of a second conductivity type opposite to that of the substrate; and boring similar holes on the upper surface side of the substrate to define an isolating wall and diffuse from these holes a dopant of the second conductivity type with a high doping level, the holes corresponding to the isolating wall being sufficiently close for the diffused areas to join laterally and vertically.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: June 17, 2003
    Assignee: STMicroelectronics S.A.
    Inventor: Mathieu Roy
  • Publication number: 20010054739
    Abstract: A power component formed in an N-type silicon substrate, the lower and upper surfaces of which respectively include a first and a second P-type region that do not extend to the component periphery, a high voltage being capable of existing between the first and second regions and having to be withstood by the junctions between the first and second regions and the substrate. A deep insulating region that does not join the first region is provided at the lower periphery of the component, the lower surface of the substrate between said deep insulating region and the first region being coated with an insulating layer, the height of the deep insulating region being greater than that of a possible soldering upward extension formed during the soldering of the lower surface on a heat sink.
    Type: Application
    Filed: May 15, 2001
    Publication date: December 27, 2001
    Inventor: Mathieu Roy
  • Patent number: 6326648
    Abstract: A monolithic power switch with a controlled di/dt including the parallel assembly of a MOS or IGBT type component with a thyristor type component, including means for inhibiting the thyristor type component during the closing phase of the switch, which is ensured by the IGBT type component. The IGBT type component has a vertical multicell structure and the component of thyristor type has a vertical monocell structure.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: December 4, 2001
    Assignee: STMicroelectronics S.A.
    Inventors: Jean Jalade, Jean-Louis Sanchez, Jean-Pierre Laur, Marie Breil, Patrick Austin, Eric Bernier, Mathieu Roy