Abstract: A packet processor whose processing capabilities are optimized by concurrently processing multiple packets within various pipelined stages. At each stage, multiple packets are processed via an internally pipelined sub-processor. In one embodiment, the packets are processed in a round robin fashion. When a particular packet is done processing at a particular stage, it may pass another packet whose processing is not complete, and move to a next stage. In another embodiment, a packet is processed until a conditional branch instruction or any other instruction causing a potential stall is encountered. If such an instruction is encountered, a next available packet is selected and processed instead of wasting processing cycles during the stall, or proceeding with the processing of the current packet based on a predicted result. The sub-processor resumes processing of the packet once the stall is over.

Abstract: A packet processor whose processing capabilities are optimized by concurrently processing multiple packets within various pipelined stages. At each stage, multiple packets are processed via an internally pipelined sub-processor. In one embodiment, the packets are processed in a round robin fashion. When a particular packet is done processing at a particular stage, it may pass another packet whose processing is not complete, and move to a next stage. In another embodiment, a packet is processed until a conditional branch instruction or any other instruction causing a potential stall is encountered. If such an instruction is encountered, a next available packet is selected and processed instead of wasting processing cycles during the stall, or proceeding with the processing of the current packet based on a predicted result. The sub-processor resumes processing of the packet once the stall is over.

Abstract: A packet processor whose processing capabilities are optimized by concurrently processing multiple packets within various pipelined stages. At each stage, multiple packets are processed via an internally pipelined sub-processor. In one embodiment, the packets are processed in a round robin fashion. When a particular packet is done processing at a particular stage, it may pass another packet whose processing is not complete, and move to a next stage. In another embodiment, a packet is processed until a conditional branch instruction or any other instruction causing a potential stall is encountered. If such an instruction is encountered, a next available packet is selected and processed instead of wasting processing cycles during the stall, or proceeding with the processing of the current packet based on a predicted result. The sub-processor resumes processing of the packet once the stall is over.

Abstract: Multiple lookup engines stacked upon one another in a single data communication switch. The lookup engine at the top of the stack transmits its result to the neighboring downstream lookup engine which either validates and transmits the received result or its own result based on the quality of its match. The result preferably indicates an exact match, partial match, or no match. Although several lookup engines can return a partial match, an exact match preferably occurs in only one lookup engine. The comparison, validation, and transmission steps are repeated by each downstream lookup engine, with the lookup engine at the bottom of the stack validating and returning a final result to the packet processor. The returned final result reflects a search result with the highest match quality.

Abstract: A switch includes a backplane and multiple packet processors. One or more packet processors include multi-level policing logic. The packet processor receives a packet and classifies the packet into multiple policeable groups. The packet is compared against bandwidth contracts defined for the policeable groups. Nested lookups are performed for the packet in a policing database to identify the multiple groups and to retrieve policing data for the multiple policeable groups. The policing results, which may be combined into a single policing result by taking the worst case policing result, are applied to disposition logic as recommendations, and are combined with other disposition recommendations to make a disposition decision for the packet.

Abstract: A packet processor whose processing capabilities are optimized by concurrently processing multiple packets within various pipelined stages. At each stage, multiple packets are processed via an internally pipelined sub-processor. In one embodiment, the packets are processed in a round robin fashion. When a particular packet is done processing at a particular stage, it may pass another packet whose processing is not complete, and move to a next stage. In another embodiment, a packet is processed until a conditional branch instruction or any other instruction causing a potential stall is encountered. If such an instruction is encountered, a next available packet is selected and processed instead of wasting processing cycles during the stall, or proceeding with the processing of the current packet based on a predicted result. The sub-processor resumes processing of the packet once the stall is over.

Abstract: A packet switching node has first and second forwarding engines interconnected over a first path dependent on an inspection engine and a second path independent of the inspection engine. The first forwarding engine identifies a first session in which an application port number is to be dynamically negotiated for a second session and directs the first session to the first path. The inspection engine monitors a dynamic application port number negotiation for the first session, determines a dynamic application port number for the second session, configures a service level for the second session on the forwarding engines and directs the second session to the second path. The first forwarding engine also identifies a third session in which an application port number is statically assigned and directs the third session to the second path.

Abstract: A data communication switch includes a backplane and multiple packet switching controllers. At least one packet switching controller includes programmable application logic for generating application data for a packet. The application logic is contained in key builder and lookup table of an application engine. The key builder contains one or more schema programs for generating keys and key controls using classification information and header data of inbound packets. The schema programs can be loaded onto the key builder during fabrication of the packet switching controller or in field. The keys and key controls are used to lookup the application data from the lookup table.

Abstract: A switch includes one or more programmable packet switching controllers. The programmable packet switching controller has a real-time edit program construction engine. The edit program construction engine receives packet data, e.g., the header data, and disposition decisions generated by, for example, an application engine. The edit program construction engine uses the packet data and the disposition decisions to construct edit programs in real-time. The edit programs include a number of instructions for performing operations, such as COPY, DELETE, RECORD, PLAYBACK, INSERT and OVERWRITE, and are stored in an instruction RAM associated with an edit engine. The edit engine executes the instructions to modify inbound packets in order to transmit them as outbound packets.

Abstract: Multiple lookup engines stacked upon one another in a single data communication switch. The lookup engine at the top of the stack transmits its result to the neighboring downstream lookup engine which either validates and transmits the received result or its own result based on the quality of its match. The result preferably indicates an exact match, partial match, or no match. Although several lookup engines can return a partial match, an exact match preferably occurs in only one lookup engine. The comparison, validation, and transmission steps are repeated by each downstream lookup engine, with the lookup engine at the bottom of the stack validating and returning a final result to the packet processor. The returned final result reflects a search result with the highest match quality.