Abstract: The present invention provides a chimeric antigen receptor (CAR) which binds a target antigen having a bulky extracellular domain, wherein the CAR comprises a Fab antigen binding domain. The present invention also provides nucleic acid sequences and constructs encoding such a CAR, cells expressing such a CAR and their therapeutic uses.

Abstract: The present invention basically relates to a closure device, in particular for a passage located in a cabin of an aircraft, comprising: a door panel; and a first carriage comprising first guide means for translationally guiding said first carriage, characterized in that said first carriage comprises second guide means for translationally guiding the door panel; and a first locking system able to assume a locked state, in which the first locking system provides a mechanical connection between the door panel and the first carriage; said first locking system being able to transition to an unlocked state, in which the door panel is disengaged from the carriage.

Abstract: The invention relates to the field of motor control units, in particular those with a digital control system or unit comprising a matrix with a plurality of programmable logic units and/or being part of a platform, suitable for automotive, comprising an electric power train; and an electric power train management hardware, providing control for said electric power train, said management hardware comprising a heterogeneous hardware system comprising at least one software programmable unit (microprocessor core) and at least one motor control unit.

Abstract: The system and methods allow for emulation of random hardware failure of an internal embedded memory array of an integrated circuit (IC) device. Emulation of potential defects is performed in order to evaluate the behavior of the rest of the design. This non-intrusive emulation is performed in a pseudo-functional mode in order to evaluate the behavior of one or more memory cores in their standard functional mode. The solution enables the creation of failures and tracking both the detection of the failures and the time required time for detection. Specifically, the emulation of an internal memory array with respect of random failures and the associated diagnostic mechanism ensures that detection and correction mechanisms work as expected. A typical non-limiting use case is to ensure that safety control logic of an IC behaves as expected in cases of data corruption within an embedded memory core.

Abstract: The system and methods allow for emulation of random hardware failure of an internal embedded memory array of an integrated circuit (IC) device. Emulation of potential defects is performed in order to evaluate the behavior of the rest of the design. This non-intrusive emulation is performed in a pseudo-functional mode in order to evaluate the behavior of one or more memory cores in their standard functional mode. The solution enables the creation of failures and tracking both the detection of the failures and the time required time for detection. Specifically, the emulation of an internal memory array with respect of random failures and the associated diagnostic mechanism ensures that detection and correction mechanisms work as expected. A typical non-limiting use case is to ensure that safety control logic of an IC behaves as expected in cases of data corruption within an embedded memory core.

Abstract: The apparatus and methods allow random hardware failure emulation of an integrated circuit (IC) by emulation of potential defects to enable behavior evaluation of the rest of the design in such situation. This emulation can non-intrusively address multiple points of failure. The emulation is performed in a pseudo-functional mode in order to evaluate the IC behavior in its standard functional mode. The system allows creation of a failure, and tracking both the detection of this failure and the required time for this detection. The system further allows generation of a failure in different points of the IC, on a single or multipoint failure approaches. Failure detection and correction mechanisms for a product life cycle are therefore provided. In an embodiment the system checks the conformity of the safety function of an IC, and makes sure the safety control logic behaves as expected in case of data corruption in any register.