Abstract: This disclosure generally relates to a rectifier, a method for a rectifier, and a computer program and more specifically adjusting at least one switching time for a rectifier. In one or more embodiments, a rectifier circuit may include a first input; a first switch; an output; and an offset circuit. The rectifier circuit is configured to activate the first switch based on a first switching signal at a first time to provide an output voltage at the output. The offset circuit is configured to generate an offset current signal based on the output voltage.

Abstract: A duty cycle correction circuit (DCCC) for a multi-modulus frequency divider, the DCCC comprising: a corrector chain comprising a plurality of flip-flops each configured to receive one of the internal signals; and at least one delay selection logic element, each configured to receive an output signal from different ones of the flip-flops and the output of each delay selection logic element is based on the received output signal and the division factor; the DCCC is configured such that: a first state change in its output signal is defined by a transition to a first logic state of one of the internal signals; and a second state change in its output signal is based on a transition to a second logic state of one of the internal signals after a delay period, wherein the duty cycle of the output signal is based on the delay period.