Patents by Inventor Mathini Sellathurai

Mathini Sellathurai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Data scheduling register tree for radix-2 FFT architecture
    Patent number: 11531497
    Abstract: The present invention discloses a data scheduling register tree structure for radix-2 FFT architecture. The operation method of the proposed invention, there is no need for the Random Access Memory (RAM) to store the data; instead, shift registers with some multiplexers are enough to perform the memory operation with less hardware. There are three steps in the FFT computation such as input storage, data processing and output retrieval. The data processing step is further configured in four different operations. The number of operation mainly depends upon the size of the FFT, which is equal to log2N modes. During each operation, the DSRT changes its structure and these structures are basically MDC (Multi-path Delay Commutator) structures.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: December 20, 2022
    Assignee: National Institute of Technology
    Inventors: G. Lakshminarayanan, Antony Xavier Glittas, Mathini Sellathurai
  • DATA SCHEDULING REGISTER TREE FOR RADIX-2 FFT ARCHITECTURE
    Publication number: 20210255804
    Abstract: The present invention discloses a data scheduling register tree structure for radix-2 FFT architecture. The operation method of the proposed invention, there is no need for the Random Access Memory (RAM) to store the data; instead, shift registers with some multiplexers are enough to perform the memory operation with less hardware. There are three steps in the FFT computation such as input storage, data processing and output retrieval. The data processing step is further configured in four different operations. The number of operation mainly depends upon the size of the FFT, which is equal to log2N modes. During each operation, the DSRT changes its structure and these structures are basically MDC (Multi-path Delay Commutator) structures.
    Type: Application
    Filed: February 3, 2021
    Publication date: August 19, 2021
    Applicant: National Institute of Technology
    Inventors: G. Lakshminarayanan, Antony Xavier Glittas, Mathini Sellathurai