Abstract: Systems and methods for protecting external memory resources to prevent bandwidth collapse in a network processor. One embodiment is a network processor including an input port configured to receive packets from a source device, on-chip memory configured to store packets in queues, and external memory configured to provide a backing store to the on-chip memory. The network processor also includes a processor configured, in response to determining that the source device is unresponsive to a congestion notification, to reduce a size of one or more queues to prevent packets transferring from the on-chip memory to the external memory.

Abstract: Systems and methods for protecting external memory resources to prevent bandwidth collapse in a network processor. One embodiment is a network processor including an input port configured to receive packets from a source device, on-chip memory configured to store packets in queues, an external memory interface configured to couple the on-chip memory with an external memory providing a backing store to the on-chip memory, and bandwidth monitor configured to measure a bandwidth utilization of the external memory. The network processor also includes a processor configured to apply the bandwidth utilization of the external memory to a congestion notification profile, to generate one or more congestion notifications based on the bandwidth utilization applied to the congestion notification profile, and to send the one or more congestion notifications to the source device to request decreasing packet rate for decreasing the bandwidth utilization of the external memory.

Abstract: Systems and methods for protecting external memory resources to prevent bandwidth collapse in a network processor. One embodiment is a network processor including an input port configured to receive packets from a source device, on-chip memory configured to store packets in queues, and external memory configured to provide a backing store to the on-chip memory. The network processor also includes a processor configured, in response to determining that the source device is unresponsive to a congestion notification, to reduce a size of one or more queues to prevent packets transferring from the on-chip memory to the external memory.

Abstract: Exemplary techniques for architecture-independent dynamic flow learning in a packet forwarder are described. A packet forwarder includes a plurality of forwarding threads and a plurality of provisioning threads, and can implement three functional blocks to learn new flows—an admission control block, a forwarding database building block, and a notification path block. An admission control module can control the ability for forwarding threads to place flow operation requests in operation queues. Provisioning threads independently manage particular operation queues, and can update corresponding portions of a control database and a forwarding database. Flow operation notifications can be managed through notification queues, which can be drained back into the operation queues for the provisioning threads to later process. The packet forwarder thus can benefit from a highly-parallel, highly-efficient software-based approach to flow learning operations that does not require specialized hardware support.

Abstract: Exemplary techniques for architecture-independent dynamic flow learning in a packet forwarder are described. A packet forwarder includes a plurality of forwarding threads and a plurality of provisioning threads, and can implement three functional blocks to learn new flows—an admission control block, a forwarding database building block, and a notification path block. An admission control module can control the ability for forwarding threads to place flow operation requests in operation queues. Provisioning threads independently manage particular operation queues, and can update corresponding portions of a control database and a forwarding database. Flow operation notifications can be managed through notification queues, which can be drained back into the operation queues for the provisioning threads to later process. The packet forwarder thus can benefit from a highly-parallel, highly-efficient software-based approach to flow learning operations that does not require specialized hardware support.