Patents by Inventor Matin Amani

Matin Amani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220366991
    Abstract: An apparatus is described. An apparatus includes controller logic circuitry to perform a program-verify programming process to a flash memory chip. The program-verify programming process is to reduce a size of a pre-program verify (PPV) bucket in response to a number of cells being fully programmed to a same digital state. The number of cells are less than a total number of cells to be programmed to the same digital state.
    Type: Application
    Filed: May 14, 2021
    Publication date: November 17, 2022
    Inventors: Shantanu R. RAJWADE, Tarek Ahmed AMEEN BESHARI, Matin AMANI, Narayanan RAMANAN, Arun THATHACHARY
  • Publication number: 20220208286
    Abstract: For a nonvolatile (NV) storage media such as NAND media that is written by a program and program verify operation, the system can determine an expected number of SSPC (selective slow programming convergence) cells for a page of cells for specific conditions of the page. The system can perform program verify with a first wordline (WL) select voltage for SSPC cell detection for a first write of the page to detect the expected number of SSPC cells. Based on the determined expected number of SSPC cells, the system can set a boost voltage to capture an expected number of SSPC cells during the program verify operation. The system performs program verify for subsequent writes to the page with a higher WL select voltage, to perform program verify for standard cells and then SSPC program verify with the boost voltage determined from the first write.
    Type: Application
    Filed: December 24, 2020
    Publication date: June 30, 2022
    Inventors: Tarek Ahmed AMEEN BESHARI, Shantanu R. RAJWADE, Matin AMANI, Narayanan RAMANAN
  • Publication number: 20220172784
    Abstract: A sense circuit performs a multistage boost, including a boost during precharge operation and a boost during the standard boost operation. The sense circuit includes an output transistor to drive a sense output based on current through a sense node which drives a gate of the output transistor. The sense circuit includes a precharge circuit to precharge the sense node and the gate of the output transistor and a boost circuit to boost the sense node. The boost circuit can be boosted during precharge by a first boost voltage, resulting in a lower boost applied to the sense node after precharge. The boost circuit boosts up the sense node by a second boost voltage lower than the first boost voltage. The boost circuit boosts the sense node down by the full boost voltage of the first boost voltage plus the second boost voltage after sensing.
    Type: Application
    Filed: November 30, 2020
    Publication date: June 2, 2022
    Inventors: Shantanu R. RAJWADE, Bayan NASRI, Tzu-Ning FANG, Rezaul HAQUE, Dhanashree R. KULKARNI, Narayanan RAMANAN, Matin AMANI, Ahsanur RAHMAN, Seong Je PARK, Netra MAHULI
  • Publication number: 20210257036
    Abstract: Techniques and mechanisms for verifying the programming of a multi-bit cell of a memory array. In an embodiment, program verification is performed based on a signal, other than a word line voltage, which includes an indication of a reference voltage that is to be a basis for evaluating a currently programmed threshold voltage of a memory cell. A determination that the particular indication is to be communicated with the signal is made based on a detected state of the memory device which includes the memory cell. In another embodiment, the detected state includes one of a thermal condition at the memory array, a pressure condition at the memory array, a wear condition of the memory array, or a relative position of the cell with respect to one or more other cells of the memory array.
    Type: Application
    Filed: February 13, 2020
    Publication date: August 19, 2021
    Applicant: Intel Corporation
    Inventors: Xiang Yang, Tarek Ahmed Ameen Beshari, Narayanan Ramanan, Arun Thathachary, Shantanu Rajwade, Matin Amani
  • Patent number: 11094386
    Abstract: Techniques and mechanisms for verifying the programming of a multi-bit cell of a memory array. In an embodiment, program verification is performed based on a signal, other than a word line voltage, which includes an indication of a reference voltage that is to be a basis for evaluating a currently programmed threshold voltage of a memory cell. A determination that the particular indication is to be communicated with the signal is made based on a detected state of the memory device which includes the memory cell. In another embodiment, the detected state includes one of a thermal condition at the memory array, a pressure condition at the memory array, a wear condition of the memory array, or a relative position of the cell with respect to one or more other cells of the memory array.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: August 17, 2021
    Assignee: Intel Corporation
    Inventors: Xiang Yang, Tarek Ahmed Ameen Beshari, Narayanan Ramanan, Arun Thathachary, Shantanu Rajwade, Matin Amani
  • Patent number: 9852927
    Abstract: Two-dimensional (2D) transition-metal dichalcogenides have emerged as a promising material system for optoelectronic applications, but their primary figure-of-merit, the room-temperature photoluminescence quantum yield (QY) is extremely poor. The prototypical 2D material, MoS2 is reported to have a maximum QY of 0.6% which indicates a considerable defect density. We report on an air-stable solution-based chemical treatment by an organic superacid which uniformly enhances the photoluminescence and minority carrier lifetime of MoS2 monolayers by over two orders of magnitude. The treatment eliminates defect-mediated non-radiative recombination, thus resulting in a final QY of over 95% with a longest observed lifetime of 10.8±0.6 nanoseconds. Obtaining perfect optoelectronic monolayers opens the door for highly efficient light emitting diodes, lasers, and solar cells based on 2D materials.
    Type: Grant
    Filed: October 15, 2016
    Date of Patent: December 26, 2017
    Assignee: The Regents of the University of California
    Inventors: Matin Amani, Der-Hsien Lien, Daisuke Kiriya, James Bullock, Ali Javey
  • Publication number: 20170110338
    Abstract: Two-dimensional (2D) transition-metal dichalcogenides have emerged as a promising material system for optoelectronic applications, but their primary figure-of-merit, the room-temperature photoluminescence quantum yield (QY) is extremely poor. The prototypical 2D material, MoS2 is reported to have a maximum QY of 0.6% which indicates a considerable defect density. We report on an air-stable solution-based chemical treatment by an organic superacid which uniformly enhances the photoluminescence and minority carrier lifetime of MoS2 monolayers by over two orders of magnitude. The treatment eliminates defect-mediated non-radiative recombination, thus resulting in a final QY of over 95% with a longest observed lifetime of 10.8±0.6 nanoseconds. Obtaining perfect optoelectronic monolayers opens the door for highly efficient light emitting diodes, lasers, and solar cells based on 2D materials.
    Type: Application
    Filed: October 15, 2016
    Publication date: April 20, 2017
    Applicant: The Regents of the University of California
    Inventors: Matin Amani, Der-Hsien Lien, Daisuke Kiriya, James Bullock, Ali Javey