Abstract: A digital multiplex system has a buffer, to which a bitstream arrives at one frequency and from which a bitstream is forwarded at a different frequency. The output bitstream frequency is controlled by a phase locking circuit comprising a phase comparator, a voltage controlled oscillator and a control circuit. The buffer generates control signals indicating the phase of the pulses in the incoming bitstream and the phase of the pulses forwarded therefrom. The phase comparator receives said control signals and delivers a signal representative of the mutual phase position of the pulses in the incoming and the forwarded bitstream, the signal being fed to the control circuit for automatic gain control. The control circuit controls the pulse rate of the voltage controlled oscillator, which generates clock pulses for clocking the pulses of the forwarded bitstream. The control circuit comprises a feed-back operational amplifier.

Abstract: A circuit is provided for an oscillator circuit comprising a differential amplifier such as an ECL line receiver which directly, in one step outputs a symmetrical square wave signal. This is obtained by means of a symmetrical connection of the bias voltage to the input terminals of the ECL-line receiver through two substantially equally large resistors. A feedback loop comprises, as is conventional, a crystal and a trimming capacitor or a capacitor which may be controlled in some other way as well as a resistor. The capacitor will together with the resistor form a low-pass filter for the control of the oscillating condition of the circuit. Further, an overtone synthesizer is provided adapted to generate even multiples of the frequency of an input signal and it comprises a second ECL line receiver, the positive and negative output terminals of which are directly connected to each other.