Abstract: Determining the radial position of a first read head of a storage device includes reading servo data from a storage media platter surface using the first read head, deriving from that servo data a first positron error signal representing a first estimate of the radial position of the first read head, reading the servo data from the storage media platter surface using a different read head, deriving from that servo data a second position error signal representing an estimate of the radial position of the different read head, and combining the first estimate of the radial position of the first read head and the estimate of the radial position of the different read head to obtain a revised estimate of the radial position of the first read head. The combining could include taking account of a known positional offset between the first read head and the different read head.

Abstract: A system and method for adjusting the radial tilt, tangential tilt, or a combination of radial and tangential tilt of an optical detection unit in an optical disc reading system can include applying different weighting factors to different signal components depending on which detection area detects the component, measuring a value of a signal characteristic, such as signal-to-noise ratio, of two signals with different sets of weighting factors, and determining an adjustment factor to the radial tilt as a function of the of the measured signal characteristic values.

Abstract: A method and device for determining frequency error to extend the pull-in range of a timing recovery circuit for a storage device such as an optical disc drive. A code associated with a storage format of the storage device is detected, and the distance between occurrences of the code is determined. The calculated distance is compared with the expected distance to determine the difference. Based on the difference, the frequency error is determined.

Abstract: Aspects of the disclosure provide a method. The method includes boosting a portion of frequency components of a digital signal that is converted from an analog signal based on a clock signal, generating a decision signal based on the boosted digital signal, generating a timing error signal based on the boosted digital signal and the decision signal, and filtering the timing error signal to generate a voltage signal to control a voltage controlled oscillator to generate the clock signal.

Abstract: Devices and methods capable of controlling disc read operations are disclosed. For example, an electronic circuit can include an error-severity determining circuit configured to determine a severity of read error that occurs for a block of data read from a disc, and a re-read decision-making circuit that determines whether to re-read the block of data based on the severity of read error.

Abstract: In a method of correcting a channel bit pattern that violates bi-phase modulation constraint in a bi-phase modulated portion of a high frequency modulation (HFM) signal, a sequence of channel bits is recovered from the HFM signal. The recovered sequence of channel bits is analyzed to generate a bi-phase modulation compliant sequence of channel bits based on the recovered sequence of channel bits, wherein the bi-phase modulation compliant sequence of channel bits does not violate the bi-phase modulation constraint in the bi-phase modulated portion of the HFM signal. Bi-phase modulated HFM bits are recovered from the bi-phase modulation compliant sequence of channel bits to generate a detection output corresponding to the recovered bi-phase modulated HFM bits.

Abstract: New and useful methods and systems for detecting sync signals/patterns in streams of data are disclosed. For example, in an embodiment system for processing data includes a first module having dedicated processing circuitry configured to detect a sync signal embedded in a received stream of data and to produce an output stream of data, and second module that includes a firmware-controlled processor configured to correct sufficient errors within the received stream of data so as to allow the first module to detect the sync signal on a condition when the first module by itself is incapable of resolving the sync signal caused by the errors in the received stream of data.

Abstract: Aspects of the disclosure provide a circuit that includes a decoder, an error checking module, and a controller. The decoder is configured to receive codewords, and decode the codewords based on an error correcting code. The error checking module is configured to error-check sectors using an error detecting code in the sectors. Each sector is formed of a plurality of decoded codewords. The controller is configured to store in a memory, when the error checking fails for at least one sector, the decoded codewords and corresponding flags indicative of pass or fail of the decoding of the codewords.

Abstract: A timing jitter measurement circuit for measuring timing jitter in the digital domain may use an interpolator bank to over-sample a signal from a media reader, a zero crossing estimator to estimate a zero crossing moment in the output of the interpolator bank and a time interval analyzer (TIA) to calculate the timing jitter as the deviation of the estimated zero crossing moment from an expected zero crossing moment in a clock signal. The timing jitter measurement circuit may be integrated into digital circuitry since it avoids using analog devices. Consequently, it may simplify the chip design, lower power consumption and save space.

Abstract: A signal processing circuit includes a plurality of processing-circuit modules and a logic control circuit. The plurality of processing-circuit modules is configured to process an electrical signal. The plurality of processing-circuit modules has at least one processing parameter that is adaptively adjusted based on the electrical signal. The logic control circuit is configured to receive signals from the plurality of processing-circuit modules, validate the processing based on the received signals, and control a storage circuit to sample and store a value of the processing parameter when the processing is validated. Further, the logic control circuit is configured to control the storage circuit to maintain the value of processing parameter when the processing fails validation, and to control the storage circuit to recover the processing parameter in the plurality of processing-circuit modules to the stored value when the plurality of processing-circuit modules is disturbed by a defect.

Abstract: A method and device for determining frequency error to extend the pull-in range of a timing recovery circuit for a storage device such as an optical disc drive. A code associated with a storage format of the storage device is detected, and the distance between occurrences of the code is determined. The calculated distance is compared with the expected distance to determine the difference. Based on the difference, the frequency error is determined.

Abstract: A counter is configured to generate counts associated with different locations, within a smallest addressable unit of data, on a storage medium of a disk drive. A detector is configured to detect a change in a property of a signal sensed from the storage medium. A controller is configured to: determine a count of the counter corresponding to a location, within a smallest addressable data unit on the storage medium, at which the change in the property of the signal sensed from the storage medium is detected, and change a response of at least one of the detector, a read channel controller of the disk drive, or a servo controller of the disk drive based on (i) the count and (ii) the counter.

Abstract: Aspects of the disclosure provide a method. The method includes receiving regional quality information of a region on a storage medium, and adjusting a fill level threshold of a buffer based on the regional quality information. The fill level threshold is used to trigger filling the buffer with data read from the region.

Abstract: Methods and systems for compensating reducing jitter produced by a phase-locked loop are disclosed. For example, in a particular embodiment, a phase-locked loop device for reducing jitter may include a voltage-control oscillator (VCO) signal configured to produce a VCO signal, phase-detection circuitry configured to compare an input signal and the VCO signal to produce a phase error signal, and slew-rate limiting circuitry configured to receive the phase error signal and apply a slew-rate limit process on the phase error signal to produce a modified error signal.

Abstract: Aspects of the disclosure provide a signal processing circuit. The signal processing circuit includes a processing path and a zero-start module. The processing path is configured to process an electrical signal that is generated in response to reading data on a storage medium. The data includes at least a first field and a second field. The electrical signal has a first profile corresponding to the first field and has a second profile corresponding to the second field. The zero-start module is configured to detect a field change from the first field to the second field, and control the processing path to add a compensation as a function of a profile change from the first profile to the second profile to keep the processed electrical signal to have a predetermined profile in response to the detected field change.

Abstract: New and useful methods and systems for providing improved performance of a Viterbi device are disclosed. For example, in an embodiment a Viterbi device includes metric circuitry configured to determine branch metrics using at least one of a variance signal based on both received data and detected data of the Viterbi device and a priori probabilities of available state transitions within a trellis of the Viterbi device.

Abstract: Systems and techniques relating to interpreting signals on a noisy channel. A direct current (DC) correction can be applied to an input of a post processor outside of a main read path that supplies data detector output to the post processor. A signal processing apparatus can include a data detector, a post processor responsive to an output of the data detector, and one or more DC control units configured and arranged to apply a first DC correction to an input of the data detector and a second DC correction to an input of the post processor, wherein the second DC correction is different from the first DC correction.

Abstract: New and useful methods and systems for detecting sync signals/patterns in streams of data are disclosed. For example, in an embodiment system for processing data includes a first module having dedicated processing circuitry configured to detect a sync signal embedded in a received stream of data and to produce an output stream of data, and second module that includes a firmware-controlled processor configured to correct sufficient errors within the received stream of data so as to allow the first module to detect the sync signal on a condition when the first module by itself is incapable of resolving the sync signal caused by the errors in the received stream of data.

Abstract: According to an aspect of the present disclosure, a system for correcting for DC characteristics of a magnetic recording system includes: circuitry implementing at least a portion of a write channel of the magnetic recording system; and circuitry configured to process output data of the write channel circuitry in accordance with a read channel of the magnetic recording system and repeatedly trigger re-writing through the write channel circuitry using different ones of a plurality of available data scramblings until a measured baseline wander exceeds a target threshold.

Abstract: A decoder including a decode module, a matrix module, and a marking module. The decode module receives data and performs a first decoding iteration to decode the data. The first decoding iteration includes generating a first matrix having a first byte. The matrix module generates a second matrix based on the first matrix. The second matrix includes the first and second bytes. The second byte is adjacent and sequentially prior or subsequent to the first byte. The marking module: determines whether the first byte has been correctly decoded; based on determining whether the first byte has been correctly decoded, determines a status of the second byte; and based on the status of the second byte, marks the first byte as an erasure. The decode module, based on the second byte being marked as an erasure, corrects the second byte during the second decoding iteration.