Abstract: In a differential line receiver circuit having differential amplifier circuit where output rise and fall times are influenced by the ability of internal current sources to charge parasitic capacitances, a feedback circuit is provided to tune those current sources so as to deliver equal rise and fall time on both outputs. According to one embodiment a detector signal is derived from timing errors resulting from such rise and fall time discrepancies by means of a nested CMOS inverter arrangement coupled to an integrating element, and then used to control one or both of said current sources.

Abstract: In a differential line receiver circuit having differential amplifier circuit where output rise and fall times are influenced by the ability of internal current sources to charge parasitic capacitances, a feedback circuit is provided to tune those current sources so as to deliver equal rise and fall time on both outputs. According to one embodiment a detector signal is derived from timing errors resulting from such rise and fall time discrepancies by means of a nested CMOS inverter arrangement coupled to an integrating element, and then used to control one or both of said current sources.

Abstract: A differential signal transfer circuit to control the common mode level of a differential signal, comprising an input common mode level detection circuit, for detecting the common mode level of an incoming signal, two capacitors coupled between the first input and output and the second input and output respectively, and a control circuit adapted to control an output common mode voltage level at the output terminals by controlling the levels of charge on the two capacitors dependent on the common mode level of the incoming signal as detected by the input common mode detector.

Abstract: A digital line driver circuit 1 for driving a transmission line and being arranged to receive a digital input signal Di and output a digital output signal in accordance with said digital input signal Di, said digital line driver circuit being operable in at least a first and a second mode in accordance with a mode selection signal Pe, wherein said first mode is a signal relay mode in which said digital output signal follows said digital input signal, and said second mode is a pre-emphasis mode in which said digital output signal follows said digital input signal and has an additional predetermined distortion.

Abstract: A differential signal transfer circuit to control the common mode level of a differential signal, comprising an input common mode level detection circuit (40), for detecting the common mode level of an incoming signal, two capacitors (60, 61) coupled between the first input and output and the second input and output respectively, and a control circuit (50) adapted to control an output common mode voltage level at the output terminals (20, 21) by controlling the levels of charge on the (60, 61) dependent on the common mode level of the incoming signal as detected by the input common mode detector (40).

Abstract: A digital line driver circuit 1 for driving a transmission line and being arranged to receive a digital input signal Di and output a digital output signal in accordance with said digital input signal Di, said digital line driver circuit being operable in at least a first and a second mode in accordance with a mode selection signal Pe, wherein said first mode is a signal relay mode in which said digital output signal follows said digital input signal, and said second mode is a pre-emphasis mode in which said digital output signal follows said digital input signal and has an additional predetermined distortion.

Abstract: A connecting arrangement includes a number of NMOS transistors that can be activated or deactivated by means of a control voltage, serving as a control signal, connected to the gate terminals of transistors, to be able to form a circuit connected between two conductors, the circuit presenting resistive properties. The circuit is equipped with a signal receiver and it is regulated by an analog control voltage. The control voltage is connectable to one or several of a number of available control connections. Each control connection is connected to the gate terminals of a group of transistors where the drain and source terminals are connected to the conductors. The control voltage is selected so that the operating point of the transistors will be within, or at least close to, the region where the transistor presents resistive properties.

Abstract: The invention includes a terminating circuit or network (4) which is connected to a signal transmission medium in the form of one or two conductors or lines (2, 3) on which information-carrying signals in the form of voltage pulses can be transmitted, and a impedance-matching circuit (4a) connected to the conductor or conductors. The circuit includes a mean voltage value forming unit which produces a mean voltage value, a control unit, which produces adapted reference voltage value, and an impedance-matching transistor which is included in said impedance-matching circuit, wherein said voltage value and said reference voltage value are added together to form a composite control voltage which is applied to the gate-connection of the impedance matching transistor.

Abstract: A signalling system adapted for digital signals includes a signal transmitter, a signal receiver and a connection which connects the transmitter to the receiver. The transmitter includes an output buffer which has at least one transistor connected to the lowest level of a signal supply voltage, such as to "0" potential or earth potential. Driving or steering of the transistor in response to a received control signal causes the transistor to switch from a state of high impedance to a state of low impedance which exhibits resistive or at least predominantly resistive properties, such as to form an information-carrying output signal. A first of two series-connected transistors is connected to the lowest level of the signal supply voltage, for instance "0" or earth potential, and the other transistor is connected to the signal supply voltage. A connection conductor on which the information-carrying signal is transmitted is connected between the transistors.

Abstract: A delay line and clock multiplying circuit are disclosed. A plurality of phase shifters impart on a reference clock successively increasing phase shifters, wherein the phase shifters have a plurality of outputs for the successively phase shifted signals. A plurality of first AND gates combine the phase shifted signals in groups to obtain a number of pulses. The pulses are then combined in a plurality of OR gates to obtain a number of pulse signals. A clock signal generator generates, from the pulse signals, mutually time delayed clock signals. A controller is arranged to control the time delay of a delay line circuit. The controller receives at least two mutually phase shifted signals from the outputs of the phase shifters and determines a delay error. The controller then generates a control signal for the delay line circuit, the magnitude of which depends upon the delay error.