Patents by Inventor Matsumoto Toshiyuki

Matsumoto Toshiyuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Capacitance measurement method of micro structures of integrated circuits
    Patent number: 7176706
    Abstract: The present invention is a method of measuring capacitance of micro structures in an integrated circuit wherein the micro structure includes a first terminal and a second terminal separated by an insulator and at least a third terminal separated from the first terminal by an insulator. The method comprises applying biasing voltage to the second terminal and applying the same potential to the first and third terminals. An electrical characteristic between the first and second terminals are measured to determined the capacitance between the first and second terminals.
    Type: Grant
    Filed: June 7, 2005
    Date of Patent: February 13, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Matsumoto Toshiyuki, Yakabe Masami, Hirota Yoshihiro
  • Capacitance measurement method of micro structures of integrated circuits
    Publication number: 20050225350
    Abstract: The present invention is a method of measuring capacitance of micro structures in an integrated circuit wherein the micro structure includes a first terminal and a second terminal separated by an insulator and at least a third terminal separated from the first terminal by an insulator. The method comprises applying biasing voltage to the second terminal and applying the same potential to the first and third terminals. An electrical characteristic between the first and second terminals are measured to determined the capacitance between the first and second terminals.
    Type: Application
    Filed: June 7, 2005
    Publication date: October 13, 2005
    Inventors: Matsumoto Toshiyuki, Yakabe Masami, Hirota Yoshihiro
  • Capacitance measurement method of micro structures of integrated circuits
    Patent number: 6906548
    Abstract: The present invention is a method of measuring capacitance of micro structures in an integrated circuit wherein the micro structure includes a first terminal and a second terminal separated by an insulator and at least a third terminal separated from the first terminal by an insulator. The method comprises applying biasing voltage to the second terminal and applying the same potential to the first and third terminals. An electrical characteristic between the first and second terminals are measured to determined the capacitance between the first and second terminals.
    Type: Grant
    Filed: November 2, 2000
    Date of Patent: June 14, 2005
    Assignee: Tokyo Electron Limited
    Inventors: Matsumoto Toshiyuki, Yakabe Masami, Hirota Yoshihiro