Patents by Inventor Matt Davidson
Matt Davidson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11880603Abstract: A storage system receives a command from a host to overwrite data that is stored in a memory of the storage system. The command may have been issued in error or by malware, so the storage system preserves the data that the host wants to overwrite, just in case the host later wants to recover the data. To do this, the storage system associates the physical address of the location of the memory that stores the data with a logical block address that is inaccessible by the host. To recover the data, the storage system replaces the logical block address that is inaccessible by the host with a logical block address that is accessible by the host.Type: GrantFiled: April 20, 2022Date of Patent: January 23, 2024Assignee: Western Digital Technologies, Inc.Inventors: Nicholas Thomas, Eran Erez, Matt Davidson
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Publication number: 20230342078Abstract: A storage system receives a command from a host to overwrite data that is stored in a memory of the storage system. The command may have been issued in error or by malware, so the storage system preserves the data that the host wants to overwrite, just in case the host later wants to recover the data. To do this, the storage system associates the physical address of the location of the memory that stores the data with a logical block address that is inaccessible by the host. To recover the data, the storage system replaces the logical block address that is inaccessible by the host with a logical block address that is accessible by the host.Type: ApplicationFiled: April 20, 2022Publication date: October 26, 2023Applicant: Western Digital Technologies, Inc.Inventors: Nicholas Thomas, Eran Erez, Matt Davidson
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Publication number: 20170185277Abstract: Systems and methods include an automation network comprising a gateway located at/in a premises. The gateway is coupled to a remote network and is configured to control components at the premises including premises devices and a security system comprising security system components. The components include at least one camera. A sensor user interface (SUI) is coupled to the gateway and presented to a user via remote client devices. The SUI includes display elements for managing and receiving data of the premises components agnostically across the remote client devices. The display elements include a timeline user interface comprising event data of the components positioned at a time corresponding to events.Type: ApplicationFiled: August 16, 2016Publication date: June 29, 2017Inventors: Ken SUNDERMEYER, Jim FULKER, Matt DAVIDSON, Paul DAWES
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Patent number: 9430411Abstract: Apparatus and methods implemented therein are disclosed for communicating with flash memories. The apparatus comprises a flash interface module and a processor in communication with the flash interface module. The flash interface module is configured for communication with a first and second flash bank. The processor is configured to generate a plurality of command sequences in response to receiving a plurality of flash commands from a host system. Each of the plurality of command sequences corresponds to a respective one of the plurality of flash commands. Some of the plurality of command sequences comprises a first portion and a second portion and each of the first portion and second portion are atomic.Type: GrantFiled: November 13, 2013Date of Patent: August 30, 2016Assignee: SanDisk Technologies LLCInventors: Gary Lin, Matt Davidson, Milton Barrocas, Aruna Gutta
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Publication number: 20150134884Abstract: Apparatus and methods implemented therein are disclosed for communicating with flash memories. The apparatus comprises a flash interface module and a processor in communication with the flash interface module. The flash interface module is configured for communication with a first and second flash bank. The processor is configured to generate a plurality of command sequences in response to receiving a plurality of flash commands from a host system. Each of the plurality of command sequences corresponds to a respective one of the plurality of flash commands. Some of the plurality of command sequences comprises a first portion and a second portion and each of the first portion and second portion are atomic.Type: ApplicationFiled: November 13, 2013Publication date: May 14, 2015Inventors: Gary Lin, Matt Davidson, Milton Barrocas, Aruna Gutta
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Patent number: 8984203Abstract: First and second data interfaces provide data transfer to and from a plurality of memory banks. The first data interface uses a first bus size and a first clock frequency. The second data interface uses a second bus size and a second clock frequency. The second bus size is an integer multiple of the first bus size. The first clock frequency is an integer multiple of the second clock frequency. A channelizer module segments data from the second data interface into data segments of the first bus size and transmits them to addressed ones of the plurality of memory banks using the first clock frequency. The channelizer module also receives data in accordance with the first bus size and first clock frequency from the plurality of memory banks, combines this data into the second bus size, and transmits the data to the second data interface using the second clock frequency.Type: GrantFiled: October 9, 2012Date of Patent: March 17, 2015Assignee: SanDisk Technologies Inc.Inventors: Baojing Liu, Matt Davidson, Aruna Gutta
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Publication number: 20140101354Abstract: First and second data interfaces provide data transfer to and from a plurality of memory banks. The first data interface uses a first bus size and a first clock frequency. The second data interface uses a second bus size and a second clock frequency. The second bus size is an integer multiple of the first bus size. The first clock frequency is an integer multiple of the second clock frequency. A channelizer module segments data from the second data interface into data segments of the first bus size and transmits them to addressed ones of the plurality of memory banks using the first clock frequency. The channelizer module also receives data in accordance with the first bus size and first clock frequency from the plurality of memory banks, combines this data into the second bus size, and transmits the data to the second data interface using the second clock frequency.Type: ApplicationFiled: October 9, 2012Publication date: April 10, 2014Inventors: Baojing Liu, Matt Davidson, Aruna Gutta
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Patent number: 8266485Abstract: A soft-function trigger state machine includes state machine logic defined to use a scan-in waveform to sample a scan-clock waveform to obtain a sampled data pattern. The state machine logic is defined to compare the sampled data pattern to a soft action pattern to determine whether the sampled data pattern matches the soft action pattern. The state machine logic is also defined to trigger an action associated with the soft action pattern when the sampled data pattern matches the soft action pattern.Type: GrantFiled: June 13, 2011Date of Patent: September 11, 2012Assignee: SanDisk Technologies Inc.Inventors: Baojing Liu, Matt Davidson, Vladimir Kovalev
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Publication number: 20110246844Abstract: A soft-function trigger state machine includes state machine logic defined to use a scan-in waveform to sample a scan-clock waveform to obtain a sampled data pattern. The state machine logic is defined to compare the sampled data pattern to a soft action pattern to determine whether the sampled data pattern matches the soft action pattern. The state machine logic is also defined to trigger an action associated with the soft action pattern when the sampled data pattern matches the soft action pattern.Type: ApplicationFiled: June 13, 2011Publication date: October 6, 2011Applicant: SanDisk CorporationInventors: Baojing Liu, Matt Davidson, Vladimir Kovalev
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Patent number: 7962819Abstract: An integrated circuit chip includes a scan-in pin, a scan clock pin, and a test controller. The scan-in pin and the scan clock pin receive a test program for the type of test mode and a soft-reset pattern. A state machine is configured to direct sampling of a scan clock waveform provided through the scan clock pin as dictated by transitions of a scan-in waveform provided through the scan-in pin. The state machine identifies a bit match from the sampled scan clock waveform upon executing the soft-reset pattern. The identified bit match triggers a soft reset which eliminates the need for an extra reset pin, when testing in scan mode.Type: GrantFiled: January 24, 2008Date of Patent: June 14, 2011Assignee: SanDisk CorporationInventors: Baojing Liu, Matt Davidson, Vladimir Kovalev
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Publication number: 20090193305Abstract: An integrated circuit chip having testing logic for testing circuitry of the integrated circuit chip is provided. The integrated circuit chip includes at least a scan-in pin, a scan clock pin, and a test controller. The test controller has test mode registers for storing a type of test mode to be executed, and the test controller accepting signals from the scan-in pin and the scan clock pin. The scan-in pin and the scan clock pin receiving a test program for the type of test mode and a soft-reset pattern. Also included is a state machine logic that is part of the integrated circuit chip. The state machine logic, during execution of the test program, being configured to direct sampling of a scan clock waveform provided through the scan clock pin as dictated by transitions of a scan-in waveform provided through the scan-in pin. The sampling by the state machine circuitry identifying a bit match from the sampled scan clock waveform upon executing the soft-reset pattern.Type: ApplicationFiled: January 24, 2008Publication date: July 30, 2009Applicant: SanDisk CorporationInventors: Baojing Liu, Matt Davidson, Vladimir Kovalev
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Publication number: 20050155943Abstract: A system and/or apparatus (A) is provided for organizing and displaying wallcovering samples (30). The system (A) includes: a plurality of wallcovering samples (30), each sample having a color characteristics; and, a plurality of sample holders (20), each holder (20) being dedicated to a different color group and configured to hold a set of the samples (30); wherein the samples (30) are organized into the holders (20) based upon their respective color characteristics such that each holder (20) holds a set of samples (30) having like color characteristics.Type: ApplicationFiled: January 15, 2004Publication date: July 21, 2005Applicant: RJF International CorporationInventors: John Butcher, Stephanie Segall-Butcher, Matt Davidson