Patents by Inventor Matt Willis

Matt Willis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods of fabricating transistors having buried P-type layers coupled to the gate
    Patent number: 7943972
    Abstract: A unit cell of a metal-semiconductor field-effect transistor (MESFET) is provided. The MESFET has a source, a drain and a gate. The gate is between the source and the drain and on an n-type conductivity channel layer. A p-type conductivity region is provided beneath the gate between the source and the drain. The p-type conductivity region is spaced apart from the n-type conductivity channel layer and electrically coupled to the gate. Related methods are also provided herein.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: May 17, 2011
    Assignee: Cree, Inc.
    Inventors: Saptharishi Sriram, Matt Willis
  • Methods of Fabricating Transistors Having Buried P-Type Layers Coupled to the Gate
    Publication number: 20100072520
    Abstract: A unit cell of a metal-semiconductor field-effect transistor (MESFET) is provided. The MESFET has a source, a drain and a gate. The gate is between the source and the drain and on an n-type conductivity channel layer. A p-type conductivity region is provided beneath the gate between the source and the drain. The p-type conductivity region is spaced apart from the n-type conductivity channel layer and electrically coupled to the gate. Related methods are also provided herein.
    Type: Application
    Filed: November 30, 2009
    Publication date: March 25, 2010
    Inventors: Saptharishi Sriram, Matt Willis
  • Transistors having buried p-type layers coupled to the gate
    Patent number: 7646043
    Abstract: A unit cell of a metal-semiconductor field-effect transistor (MESFET) is provided. The MESFET has a source, a drain and a gate. The gate is between the source and the drain and on an n-type conductivity channel layer. A p-type conductivity region is provided beneath the gate between the source and the drain. The p-type conductivity region is spaced apart from the n-type conductivity channel layer and electrically coupled to the gate. Related methods are also provided herein.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: January 12, 2010
    Assignee: Cree, Inc.
    Inventors: Saptharishi Sriram, Matt Willis
  • TRANSISTORS HAVING BURIED P-TYPE LAYERS COUPLED TO THE GATE AND METHODS OF FABRICATING THE SAME
    Publication number: 20080079036
    Abstract: A unit cell of a metal-semiconductor field-effect transistor (MESFET) is provided. The MESFET has a source, a drain and a gate. The gate is between the source and the drain and on an n-type conductivity channel layer. A p-type conductivity region is provided beneath the gate between the source and the drain. The p-type conductivity region is spaced apart from the n-type conductivity channel layer and electrically coupled to the gate. Related methods are also provided herein.
    Type: Application
    Filed: September 28, 2006
    Publication date: April 3, 2008
    Inventors: Saptharishi Sriram, Matt Willis
  • Bottle
    Patent number: D1034207
    Type: Grant
    Filed: February 10, 2023
    Date of Patent: July 9, 2024
    Assignee: S. C. Johnson & Son, Inc.
    Inventors: Shabistan Sheerin, Matt Willis, Lulu McFayden Mills, Daniel Grossman, Monica Elizabeth Wright
  • Bottle
    Patent number: D1050903
    Type: Grant
    Filed: February 10, 2023
    Date of Patent: November 12, 2024
    Assignee: S. C. Johnson & Son, Inc
    Inventors: Shabistan Sheerin, Matt Willis, Lulu McFayden Mills, Daniel Grossman, Monica Elizabeth Wright