Abstract: Controllers, systems and methods are presented related to resonant converters. In case of a load imbalance between the resonant converters, an on-time of a synchronous rectifier switch of one of the resonant converters is reduced.

Abstract: In an embodiment, a DC-DC power conversion circuit with a step-down conversion ratio of at least 12:1 is provided. The DC-DC power conversion circuit includes a half-bridge circuit arrangement, a resonant capacitor and a module including a hybrid transformer. The hybrid transformer includes a magnetic core and a primary winding electrically coupled in series with a secondary winding. The module further includes a synchronous rectifier having an output coupled between the primary winding and the secondary winding of the hybrid transformer, and an output capacitor coupled with an output of the secondary winding.

Abstract: An LLC converter has a primary side with power switch devices coupled to an LLC tank circuit at a common node, a secondary side with synchronous rectifier switch devices, and a transformer coupling the primary side to the secondary side. In a first mode of operation, the power switch devices and the synchronous rectifier switch devices are switched at a frequency calculated to regulate an output voltage of the LLC converter. In a second mode of operation during light-load conditions in which the output voltage is unregulated, the power switch devices are switched until the output voltage rises to a first level and then turned off until the output voltage falls to a second level below the first level. The synchronous rectifier switch devices are continuously switched in the second mode of operation, irrespective of the state of the output voltage.

Abstract: A method for operating a switched mode power supply (SMPS) during a start-up sequence includes receiving an input current at a bias supply circuit while a first relay and a second relay coupled to a first side circuit within the SMPS are open, generating a first bias supply voltage based on the received input current, closing the first relay after generating the first bias supply voltage, conducting the input current through the first relay and through an in-rush resistor coupled in series with the first relay, and closing the second relay after a first time period.

Abstract: A device includes a driver circuit, a first semiconductor chip monolithically integrated with the driver circuit in a first semiconductor material, and a second semiconductor chip integrated in a second semiconductor material. The second semiconductor material is a compound semiconductor.

Abstract: In accordance with an embodiment, a method includes conducting a reverse current through a first switch that includes a normally-on transistor coupled in series with a normally-off transistor between a first switch node and a second switch node. While conducting the reverse current, the first switch is turned-off by turning-off the normally-off transistor via a control node of the normally-off transistor and reducing a drive voltage of the normally-on transistor by decreasing a voltage between the control node of the normally-on transistor and a reference node of the normally-on transistor. After turning-off the first switch, a second switch coupled to the first switch is turned on.

Abstract: A package comprising an electronic chip, a laminate type encapsulant in and/or on which the electronic chip is mounted, a solderable electric contact on a solder surface of the package, and a solder flow path on and/or in the package which is configured so that, upon soldering the electric contact with a mounting base, part of solder material flows along the solder flow path towards a surface of the package at which the solder material is optically inspectable after completion of the solder connection between the mounting base and the electric contact.

Abstract: In accordance with an embodiment, a method includes driving a transistor device by a driver having an output coupled to a control node of the transistor through a capacitor and limiting a magnitude of a voltage of one polarity between the control node and a first load node of the transistor device by a rectifier circuit.

Abstract: A device includes a first semiconductor chip that is arranged over a first carrier and includes a first electrical contact. The device further includes a second semiconductor chip arranged over a second carrier and including a second electrical contact arranged over a surface of the second semiconductor chip facing the second carrier. The second carrier is electrically coupled to the first electrical contact and the second electrical contact.

Abstract: In accordance with an embodiment, a method includes conducting a reverse current through a first switch that includes a normally-on transistor coupled in series with a normally-off transistor between a first switch node and a second switch node. While conducting the reverse current, the first switch is turned-off by turning-off the normally-off transistor via a control node of the normally-off transistor and reducing a drive voltage of the normally-on transistor by decreasing a voltage between the control node of the normally-on transistor and a reference node of the normally-on transistor. After turning-off the first switch, a second switch coupled to the first switch is turned on.

Abstract: In accordance with an embodiment, a method includes driving a transistor device by a driver having an output coupled to a control node of the transistor through a capacitor and limiting a magnitude of a voltage of one polarity between the control node and a first load node of the transistor device by a rectifier circuit.

Abstract: In an embodiment, an electronic component includes a high-voltage depletion mode transistor including a current path coupled in series with a current path of a low-voltage enhancement mode transistor, a diode including an anode and a cathode, and a die pad. A rear surface of the high-voltage depletion mode transistor is mounted on and electrically coupled to the die pad. A first current electrode of the low-voltage enhancement mode transistor is mounted on and electrically coupled to the die pad. The anode of the diode is coupled to a control electrode of the high-voltage depletion mode transistor, and the cathode of the diode is mounted on the die pad.

Abstract: A method for operating a switched mode power supply (SMPS) during a start-up sequence includes receiving an input current at a bias supply circuit while a first relay and a second relay coupled to a first side circuit within the SMPS are open, generating a first bias supply voltage based on the received input current, closing the first relay after generating the first bias supply voltage, conducting the input current through the first relay and through an in-rush resistor coupled in series with the first relay, and closing the second relay after a first time period.

Abstract: A device includes a first semiconductor chip that is arranged over a first carrier and includes a first electrical contact. The device further includes a second semiconductor chip arranged over a second carrier and including a second electrical contact arranged over a surface of the second semiconductor chip facing the second carrier. The second carrier is electrically coupled to the first electrical contact and the second electrical contact.

Abstract: Packaged chips comprising non-integer lead pitches, systems and methods for manufacturing packaged chips are disclosed. In one embodiment a packaged device includes a first chip, a package encapsulating the first chip and a plurality of leads protruding from the package, wherein the plurality of leads comprises differing non-integer multiple lead pitches.

Abstract: Packaged chips comprising non-integer lead pitches, systems and methods for manufacturing packaged chips are disclosed. In one embodiment a packaged device includes a first chip, a package encapsulating the first chip and a plurality of leads protruding from the package, wherein the plurality of leads comprises differing non-integer multiple lead pitches.