Patents by Inventor Matteo Michel
Matteo Michel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11188379Abstract: Embodiments of the present invention disclose a method, computer program product, and system for processing a thread of execution on a plurality of independent processing cores. In various embodiments, a run state and a local maximum thermal power is assigned to each of at least part of the cores. A first one of the cores is set to the active state. The thread on the first core in the active state is processed. The processing of the thread on the first core for fulfilment of an interrupt condition is monitored. A second one of the cores is set to the active state. The processing of the thread on the first core is halted. The processing of the thread to the second core is transferred. The processing of the thread on the second core in the active state continues and the first core is set to the cooling state.Type: GrantFiled: September 21, 2018Date of Patent: November 30, 2021Assignee: International Business Machines CorporationInventors: Marco Kraemer, Matteo Michel, Carsten Otte, Christoph Raisch
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Patent number: 10838449Abstract: Automatic detection of clock grid misalignments and automatic realignment including loading a test pattern into a first storage element on a first clock grid on a circuit; scanning the test pattern from the first storage element on the first clock grid to a second storage element on a second clock grid on the circuit; reading the scanned test pattern from the second storage element on the second clock grid; evaluating the scanned test pattern for errors; and in response to detecting an error in the scanned test pattern, triggering an alignment of the first clock grid and the second clock grid.Type: GrantFiled: July 5, 2018Date of Patent: November 17, 2020Assignee: International Business Machines CorporationInventors: Benedikt Geukes, Matteo Michel, Manfred Walz
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Publication number: 20200097322Abstract: Embodiments of the present invention disclose a method, computer program product, and system for processing a thread of execution on a plurality of independent processing cores. In various embodiments, a run state and a local maximum thermal power is assigned to each of at least part of the cores. A first one of the cores is set to the active state. The thread on the first core in the active state is processed. The processing of the thread on the first core for fulfilment of an interrupt condition is monitored. A second one of the cores is set to the active state. The processing of the thread on the first core is halted. The processing of the thread to the second core is transferred. The processing of the thread on the second core in the active state continues and the first core is set to the cooling state.Type: ApplicationFiled: September 21, 2018Publication date: March 26, 2020Inventors: Marco Kraemer, Matteo Michel, Carsten Otte, Christoph Raisch
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Publication number: 20200012312Abstract: Automatic detection of clock grid misalignments and automatic realignment including loading a test pattern into a first storage element on a first clock grid on a circuit; scanning the test pattern from the first storage element on the first clock grid to a second storage element on a second clock grid on the circuit; reading the scanned test pattern from the second storage element on the second clock grid; evaluating the scanned test pattern for errors; and in response to detecting an error in the scanned test pattern, triggering an alignment of the first clock grid and the second clock grid.Type: ApplicationFiled: July 5, 2018Publication date: January 9, 2020Inventors: BENEDIKT GEUKES, MATTEO MICHEL, MANFRED WALZ
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Patent number: 10156610Abstract: A method, circuit, and design structure for an on-chip sequence profiler involves a programmable matrix and FSM in a logic circuit, a first latch receiving a scan path bit sequence and a first clock signal and generating a first output to control a select input of a first multiplexer, a first multiplexer selecting among functional path bit sequences and outputting a bit sequence to a second latch, a second latch receiving the bit sequence from the first multiplexer and a second clock signal via a second multiplexer and outputting a bit sequence to a logic circuit, a logic circuit receiving the bit sequence from the second latch and outputting a clock control signal to the clock and a second selector control signal to the second multiplexer, and a second multiplexer receiving a second clock signal from the clock and outputting the second clock signal to the second latch.Type: GrantFiled: May 3, 2017Date of Patent: December 18, 2018Assignee: International Business Machines CorporationInventors: Benedikt Geukes, Manfred Walz, Matteo Michel
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Publication number: 20180321314Abstract: A method, circuit, and design structure for an on-chip sequence profiler involves a programmable matrix and FSM in a logic circuit, a first latch receiving a scan path bit sequence and a first clock signal and generating a first output to control a select input of a first multiplexer, a first multiplexer selecting among functional path bit sequences and outputting a bit sequence to a second latch, a second latch receiving the bit sequence from the first multiplexer and a second clock signal via a second multiplexer and outputting a bit sequence to a logic circuit, a logic circuit receiving the bit sequence from the second latch and outputting a clock control signal to the clock and a second selector control signal to the second multiplexer, and a second multiplexer receiving a second clock signal from the clock and outputting the second clock signal to the second latch.Type: ApplicationFiled: May 3, 2017Publication date: November 8, 2018Inventors: Benedikt Geukes, Manfred Walz, Matteo Michel
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Publication number: 20180321315Abstract: A method, circuit, and design structure for an on-chip sequence profiler involves a programmable matrix and FSM in a logic circuit, a first latch receiving a scan path bit sequence and a first clock signal and generating a first output to control a select input of a first multiplexer, a first multiplexer selecting among functional path bit sequences and outputting a bit sequence to a second latch, a second latch receiving the bit sequence from the first multiplexer and a second clock signal via a second multiplexer and outputting a bit sequence to a logic circuit, a logic circuit receiving the bit sequence from the second latch and outputting a clock control signal to the clock and a second selector control signal to the second multiplexer, and a second multiplexer receiving a second clock signal from the clock and outputting the second clock signal to the second latch.Type: ApplicationFiled: December 7, 2017Publication date: November 8, 2018Inventors: Benedikt Geukes, Manfred Walz, Matteo Michel
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Patent number: 9727754Abstract: Some embodiments include a method for processing a scan chain in an integrated circuit, the method comprising receiving, in the integrated circuit, the scan chain, wherein the scan chain includes a secret key pattern; separating the secret key pattern from the scan chain; storing the scan chain in a first plurality of latches; storing the secret key pattern in a second plurality of latches; comparing the secret key pattern to a reference key pattern, the reference key pattern stored in a third plurality of latches; determining, based on the comparing the secret key pattern to the reference key pattern, that the secret key pattern does not match the reference key pattern; and generating a signal indicating that the secret key pattern does not match the reference key pattern.Type: GrantFiled: November 18, 2015Date of Patent: August 8, 2017Assignee: International Business Machines CorporationInventors: Benedikt Geukes, Bodo Hoppe, Matteo Michel, Juergen Wakunda
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Publication number: 20160070933Abstract: Some embodiments include a method for processing a scan chain in an integrated circuit, the method comprising receiving, in the integrated circuit, the scan chain, wherein the scan chain includes a secret key pattern; separating the secret key pattern from the scan chain; storing the scan chain in a first plurality of latches; storing the secret key pattern in a second plurality of latches; comparing the secret key pattern to a reference key pattern, the reference key pattern stored in a third plurality of latches; determining, based on the comparing the secret key pattern to the reference key pattern, that the secret key pattern does not match the reference key pattern; and generating a signal indicating that the secret key pattern does not match the reference key pattern.Type: ApplicationFiled: November 18, 2015Publication date: March 10, 2016Inventors: Benedikt Geukes, Bodo Hoppe, Matteo Michel, Juergen Wakunda
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Patent number: 9222973Abstract: Some embodiments include a method for processing a scan chain in an integrated circuit. The method can include: receiving, in the integrated circuit, the scan chain, wherein the scan chain includes a secret key pattern; separating the secret key pattern from the scan chain; comparing the secret key pattern to a reference key pattern; determining, based on the comparing the secret key pattern to the reference key pattern, that the secret key pattern does not match the reference key pattern; and generating a signal indicating that the secret key pattern does not match the reference key pattern.Type: GrantFiled: January 20, 2012Date of Patent: December 29, 2015Assignee: International Business Machines CorporationInventors: Benedikt Geukes, Bodo Hoppe, Matteo Michel, Juergen Wakunda
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Patent number: 9202060Abstract: The present invention relates to a method for a self-boot of an electronic device, wherein an external component is accessible through an interface of the electronic device (101), the method comprising, determining a boot mode for booting the electronic device, wherein the determined boot mode is defined as a secure boot mode; disabling the interface, thereby prohibiting access to the component through the interface, thereby defining a secure state of the electronic device; loading a first code comprising a sequence of executable instructions to be executed for booting the electronic device; loading a second code, the second code being encrypted; and decrypting the second code and executing the second code, thereby enabling the interface, and switching the electronic device from the secure state to a debugging state.Type: GrantFiled: December 6, 2012Date of Patent: December 1, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Benedikt Geukes, Heiko Michel, Matteo Michel, Manfred Walz
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Patent number: 9110137Abstract: A scan circuit (JTAG 1149 extension) for a microprocessor utilizes transport logic and scan chains which operate at a faster clock speed than the external JTAG clock. The transport logic converts the input serial data stream (TDI) into input data packets which are sent to scan chains, and converts output data packets into an output data stream (TDO). The transport logic includes a deserializer having a sliced input buffer, and a serializer having a sliced output buffer. The scan circuit can be used for testing with boundary scan latches, or to control internal functions of the microprocessor. Local clock buffers can be used to distribute the clock signals, controlled by thold signals generated from oversampling of the external clock. The result is a JTAG scanning system which is not limited by the external JTAG clock speed, allowing multiple internal scan operations to complete within a single external JTAG cycle.Type: GrantFiled: December 3, 2013Date of Patent: August 18, 2015Assignee: International Business Machines CorporationInventors: Martin Doerr, Benedikt Geukes, Holger Horbach, Matteo Michel, Manfred Walz
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Patent number: 8984355Abstract: A technique for controlling scan access of multiple scan devices (including or more slave scan devices and a master scan device) to a scan chain includes sending, by a requesting slave scan device included in the one or more slave scan devices, a first request for access to the scan chain to the master scan device. The master scan device and the one or more slave scan devices are connected to the scan chain. The technique also includes receiving, at the requesting slave scan device, an evaluation result from the master scan device and accessing, by the requesting slave scan device, the scan chain in response to the evaluation result indicating access granted. Finally, the technique includes sending, by the requesting slave scan device, one or more second requests for access to the scan chain to the master scan device in response to the evaluation result indicating access denied.Type: GrantFiled: December 6, 2012Date of Patent: March 17, 2015Assignee: International Business Machines CorporationInventors: Benedikt Geukes, Heiko Michel, Matteo Michel, Manfred Walz
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Patent number: 8972808Abstract: A technique for controlling scan access of multiple scan devices (including or more slave scan devices and a master scan device) to a scan chain includes sending, by a requesting slave scan device included in the one or more slave scan devices, a first request for access to the scan chain to the master scan device. The master scan device and the one or more slave scan devices are connected to the scan chain. The technique also includes receiving, at the requesting slave scan device, an evaluation result from the master scan device and accessing, by the requesting slave scan device, the scan chain in response to the evaluation result indicating access granted. Finally, the technique includes sending, by the requesting slave scan device, one or more second requests for access to the scan chain to the master scan device in response to the evaluation result indicating access denied.Type: GrantFiled: March 26, 2013Date of Patent: March 3, 2015Assignee: International Business Machines CorporationInventors: Benedikt Geukes, Heiko Michel, Matteo Michel, Manfred Walz
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Patent number: 8914693Abstract: A scan circuit (JTAG 1149 extension) for a microprocessor utilizes transport logic and scan chains which operate at a faster clock speed than the external JTAG clock. The transport logic converts the input serial data stream (TDI) into input data packets which are sent to scan chains, and converts output data packets into an output data stream (TDO). The transport logic includes a deserializer having a sliced input buffer, and a serializer having a sliced output buffer. The scan circuit can be used for testing with boundary scan latches, or to control internal functions of the microprocessor. Local clock buffers can be used to distribute the clock signals, controlled by thold signals generated from oversampling of the external clock. The result is a JTAG scanning system which is not limited by the external JTAG clock speed, allowing multiple internal scan operations to complete within a single external JTAG cycle.Type: GrantFiled: February 15, 2012Date of Patent: December 16, 2014Assignee: International Business Machines CorporationInventors: Martin Doerr, Benedikt Geukes, Holger Horbach, Matteo Michel, Manfred Walz
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Publication number: 20140089749Abstract: A scan circuit (JTAG 1149 extension) for a microprocessor utilizes transport logic and scan chains which operate at a faster clock speed than the external JTAG clock. The transport logic converts the input serial data stream (TDI) into input data packets which are sent to scan chains, and converts output data packets into an output data stream (TDO). The transport logic includes a deserializer having a sliced input buffer, and a serializer having a sliced output buffer. The scan circuit can be used for testing with boundary scan latches, or to control internal functions of the microprocessor. Local clock buffers can be used to distribute the clock signals, controlled by thold signals generated from oversampling of the external clock. The result is a JTAG scanning system which is not limited by the external JTAG clock speed, allowing multiple internal scan operations to complete within a single external JTAG cycle.Type: ApplicationFiled: December 3, 2013Publication date: March 27, 2014Applicant: International Business Machines CorporationInventors: Martin Doerr, Benedikt Geukes, Holger Horbach, Matteo Michel, Manfred Walz
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Patent number: 8656235Abstract: In some embodiments, a computer-implemented method includes receiving, in a processor, a device description code identifying components of a device and connections between the components, wherein some of the components and connections form boundary cells used for testing the device. The method can include processing, in the processor, the device description code to determine that the components and the connections meet a standard governing components and connections necessary for the boundary cells. The method can also include traversing the connections between the components to determine that the connections meet the standard, and reporting, via one or more output devices, that the device complies with the standard.Type: GrantFiled: November 28, 2011Date of Patent: February 18, 2014Assignee: International Business Machines CorporationInventors: Benedikt Geukes, Matteo Michel, Carsten Schmitt, Manfred H. Walz
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Publication number: 20130212445Abstract: A scan circuit (JTAG 1149 extension) for a microprocessor utilizes transport logic and scan chains which operate at a faster clock speed than the external JTAG clock. The transport logic converts the input serial data stream (TDI) into input data packets which are sent to scan chains, and converts output data packets into an output data stream (TDO). The transport logic includes a deserializer having a sliced input buffer, and a serializer having a sliced output buffer. The scan circuit can be used for testing with boundary scan latches, or to control internal functions of the microprocessor. Local clock buffers can be used to distribute the clock signals, controlled by thold signals generated from oversampling of the external clock. The result is a JTAG scanning system which is not limited by the external JTAG clock speed, allowing multiple internal scan operations to complete within a single external JTAG cycle.Type: ApplicationFiled: February 15, 2012Publication date: August 15, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Martin Doerr, Benedikt Geukes, Holger Horbach, Matteo Michel, Manfred Walz
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Publication number: 20130139014Abstract: In some embodiments, a computer-implemented method includes receiving, in a processor, a device description code identifying components of a device and connections between the components, wherein some of the components and connections form boundary cells used for testing the device. The method can include processing, in the processor, the device description code to determine that the components and the connections meet a standard governing components and connections necessary for the boundary cells. The method can also include traversing the connections between the components to determine that the connections meet the standard, and reporting, via one or more output devices, that the device complies with the standard.Type: ApplicationFiled: November 28, 2011Publication date: May 30, 2013Applicant: International Business Machines CorporationInventors: Benedikt Geukes, Matteo Michel, Carsten Schmitt, Manfred H. Walz
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Publication number: 20120191403Abstract: Some embodiments include a method for processing a scan chain in an integrated circuit. The method can include: receiving, in the integrated circuit, the scan chain, wherein the scan chain includes a secret key pattern; separating the secret key pattern from the scan chain; comparing the secret key pattern to a reference key pattern; determining, based on the comparing the secret key pattern to the reference key pattern, that the secret key pattern does not match the reference key pattern; and generating a signal indicating that the secret key pattern does not match the reference key pattern.Type: ApplicationFiled: January 20, 2012Publication date: July 26, 2012Applicant: International Business Machines CorporationInventors: Benedikt Geukes, Bodo Hoppe, Matteo Michel, Juergen Wakunda