Abstract: Embodiments of the inventive concept include a plurality of memory ranks, a buffer chip including a rank remap control section configured to remap a rank from among the plurality of memory ranks of the volatile memory module responsive to a failure of the rank, and a dynamic serial presence detect section configured to dynamically update a stated total capacity of the volatile memory module based at least on the remapped rank. In some embodiments, a memory module includes a plurality of memory ranks, an extra rank in addition to the plurality of memory ranks, the extra rank being a spare rank configured to store a new page corresponding to a failed page from among the plurality of ranks, and a buffer chip including a page remap control section configured to remap the failed page from among the plurality of ranks to the new page in the extra rank.

Abstract: An apparatus, system, and method for controlling traffic on an on-chip network. Embodiments of the method comprise injecting a packet at a first rate into the on-chip network by a first node coupled to the on-chip network, receiving the packet at a second node coupled to the on-chip network, modifying a bit in the packet by the second node in response to determining that a rate at which packets are injected into the on-chip network should change, returning the packet with the bit modified to the first node by the second node, and changing the first rate by the first node in response to detecting that the bit in the packet was modified.

Abstract: An apparatus, system, and method for controlling traffic on an on-chip network. Embodiments of the method comprise injecting a packet at a first rate into the on-chip network by a first node coupled to the on-chip network, receiving the packet at a second node coupled to the on-chip network, modifying a bit in the packet by the second node in response to determining that a rate at which packets are injected into the on-chip network should change, returning the packet with the bit modified to the first node by the second node, and changing the first rate by the first node in response to detecting that the bit in the packet was modified.

Abstract: Some implementations provide techniques and arrangements for detecting a register value having a life longer than a threshold period based, at least in part, on at least one code segment of a code being translated by a binary translator. For a register value detected as having a life longer than a threshold period, at least one instruction to cause an access of the detected register value during the life of the register value may be included in at least one translated code segment to be output by the binary translator.

Abstract: Some implementations provide techniques and arrangements for detecting a register value having a life longer than a threshold period based, at least in part, on at least one code segment of a code being translated by a binary translator. For a register value detected as having a life longer than a threshold period, at least one instruction to cause an access of the detected register value during the life of the register value may be included in at least one translated code segment to be output by the binary translator.

Abstract: Embodiments of the inventive concept include a plurality of memory ranks, a buffer chip including a rank remap control section configured to remap a rank from among the plurality of memory ranks of the volatile memory module responsive to a failure of the rank, and a dynamic serial presence detect section configured to dynamically update a stated total capacity of the volatile memory module based at least on the remapped rank. In some embodiments, a memory module includes a plurality of memory ranks, an extra rank in addition to the plurality of memory ranks, the extra rank being a spare rank configured to store a new page corresponding to a failed page from among the plurality of ranks, and a buffer chip including a page remap control section configured to remap the failed page from among the plurality of ranks to the new page in the extra rank.

Abstract: Embodiments of systems, apparatuses, and methods for utilizing a faulty cache line in a cache are described. In some embodiments, a graphics processing unit is allowed to access a faulty cache line in the cache. A cache access request to access a faulty cache line from a central processing unit core is remapped to access a fault-free cache line.

Abstract: An online marketplace for distributing software applications is established. From the online marketplace, devices are enabled to select respective ones of the software applications and initiate testing of the selected software applications in connection with testing tools operating in respective secure testing environments that shield the devices from potential adverse effects arising from testing the selected software applications. The testing tools generate testing data relating to one or more criteria for certifying the selected software applications. For each of one or more of the selected software applications, a determination is made whether or not to classify the software application as a certified software application based on an evaluation of the testing data generated during the testing of the software applications initiated by a plurality of the devices.

Abstract: Some implementations disclosed herein provide techniques and arrangements for recovery of data stored in memory shared by a number of processors through information stored in a cache directory. A core of a processor may initiate access (e.g., read or write) to particular data located in a first cache that is accessible to the core. In response to detecting an error associated with accessing the particular data, a location in the processor that includes the particular data may be identified and the particular data may be copied from the location to the first cache.

Abstract: Embodiments of systems, apparatuses, and methods for reducing data cache power consumption and error protection overhead are described. In some embodiments, the data cache is partitioned into cache portions. Each cache portion stores data that has a different fault tolerance and uses a different type of error detection mechanism than the other cache portions.

Abstract: An integrated circuit package includes a digital logic die disposed on a substrate; and an interposer die stacked vertically with the digital logic die on the substrate. The interposer die includes at least one vertical transistor configured to selectively provide electrical power to a portion of the digital logic die.

Abstract: A method and system for tracking distributed execution on on-chip multinode networks, the method comprising: initiating, by a first node coupled to an on-chip network, execution of instructions on the first node for a distributed agent; initiating, by the first node, execution of instructions on a second node coupled to the on-chip network for the distributed agent; initiating, by the second node, execution of instructions on a third node coupled to the on-chip network for the distributed agent, wherein the second node does not notify the first node of the initiated execution on the third node; providing reoccurring notification by the second and third nodes to all nodes coupled to the on-chip network that they continue to execute instructions for the distributed agent; and determining, by the first node, that execution of instructions for the distributed agent is complete by detecting an absence of reoccurring notifications from nodes the network.

Abstract: Some implementations disclosed herein provide techniques and arrangements for recovery of data stored in memory shared by a number of processors through information stored in a cache directory. A core of a processor may initiate access (e.g., read or write) to particular data located in a first cache that is accessible to the core. In response to detecting an error associated with accessing the particular data, a location in the processor that includes the particular data may be identified and the particular data may be copied from the location to the first cache.

Abstract: Embodiments of systems, apparatuses, and methods for reducing data cache power consumption and error protection overhead are described. In some embodiments, the data cache is partitioned into cache portions. Each cache portion stores data that has a different fault tolerance and uses a different type of error detection mechanism than the other cache portions.

Abstract: An apparatus, system, and method for controlling traffic on an on-chip network. Embodiments of the method comprise injecting a packet at a first rate into the on-chip network by a first node coupled to the on-chip network, receiving the packet at a second node coupled to the on-chip network, modifying a bit in the packet by the second node in response to determining that a rate at which packets are injected into the on-chip network should change, returning the packet with the bit modified to the first node by the second node, and changing the first rate by the first node in response to detecting that the bit in the packet was modified.

Abstract: Embodiments of systems, apparatuses, and methods for utilizing a faulty cache line in a cache are described. In some embodiments, a graphics processing unit is allowed to access a faulty cache line in the cache. A cache access request to access a faulty cache line from a central processing unit core is remapped to access a fault-free cache line.

Abstract: Some implementations provide techniques and arrangements for detecting a register value having a life longer than a threshold period based, at least in part, on at least one code segment of a code being translated by a binary translator. For a register value detected as having a life longer than a threshold period, at least one instruction to cause an access of the detected register value during the life of the register value may be included in at least one translated code segment to be output by the binary translator.

Abstract: In a method for processing packets among at least a first computing device and a second computing device, in which the first computing device is configured to transmit and receive packets through a Network Interface Card (NIC), in the second computing device, descriptors of packets to be one of transmitted and received by the first computing device through a device descriptor queue are received and placed in a virtualized descriptor queue accessible by the second computing device. In addition, the packets associated with the descriptors placed in the virtualized descriptor queue are processed prior to one of transmission and receipt of the packets by the first computing device.

Abstract: A system and method is shown that includes a processor operatively connected to a memory, the processor to include a memory controller to control access to the memory. The system and method also includes a service processor, co-located on a common board and operatively connected to the processor and the memory, the service processor to include an additional memory controller to control access to the memory as part of a checkpoint regime.

Abstract: In a system for managing at least one computer node, a first device is configured to perform out-of-band operations in the at least one computing node. The system also includes a second device configured to perform compute-intensive tasks in the at least one computing node and a third device that is external to the at least one computing node configured to perform administration operations for the first device and the second device.