Abstract: A device includes a substrate and an interconnection network on the substrate. The interconnection network includes at least a first level, at least a second level and a third level. The first level includes one or more capacitors. The third level includes a metallic shield. The second level is positioned between the first level and the substrate. The capacitors of the first level are entirely separated from the substrate by the shield. The second level is located between the first and third levels.

Abstract: A modular hub driver architecture may include a multi-delay block configured to provide an enhanced delay match among N distinct stages of a distributed modulating electro-optical interface core. The electro-optical multi-core modulator driver may include an input impedance matching stage and a pre-conditioning circuit configured to generate a number M, an integer divisor of N, of delayed replicas of an electrical modulating signal. The electro-optical multi-core modulator may include an array of M launch buffers of the replica signals, and an array of M multi-delay blocks, each including delay circuit modules differently cascaded on distinct signal paths, and configured to receive, at respective inputs, the M replica signals and to output N/M differently delayed replicas of the input signals, each driving a correspondent output stage of one on the N electro-optical interface cores.

Abstract: A modular hub driver architecture may include a multi-delay block configured to provide an enhanced delay match among N distinct stages of a distributed modulating electro-optical interface core. The electro-optical multi-core modulator driver may include an input impedance matching stage and a pre-conditioning circuit configured to generate a number M, an integer divisor of N, of delayed replicas of an electrical modulating signal. The electro-optical multi-core modulator may include an array of M launch buffers of the replica signals, and an array of M multi-delay blocks, each including delay circuit modules differently cascaded on distinct signal paths, and configured to receive, at respective inputs, the M replica signals and to output N/M differently delayed replicas of the input signals, each driving a correspondent output stage of one on the N electro-optical interface cores.

Abstract: An L-C resonant circuit with an adjustable resonance frequency, having a capacitor and a first inductor electrically coupled together and a second inductor magnetically coupled to the first inductor. Additionally, there is a control circuit to sense a signal representing a first current flowing through the first inductor and to force through the second inductor a second current that is a replica of the first current for setting the adjustable resonance frequency of the L-C resonant circuit.

Abstract: An L-C resonant circuit with an adjustable resonance frequency, having a capacitor and a first inductor electrically coupled together and a second inductor magnetically coupled to the first inductor. Additionally, there is a control circuit to sense a signal representing a first current flowing through the first inductor and to force through the second inductor a second current that is a replica of the first current for setting the adjustable resonance frequency of the L-C resonant circuit.