Abstract: Apparatuses of systems that provide Safety Integration Levels (SILs) and Hardware Fault Tolerance (HFT) include a first die, the first die including first processing logic connected to a first connection and the first connection connected to second processing logic of a second die. The first die may further include a second connection to an input/output (I/O) channel where the second connection is coupled to the first processing logic. The apparatuses may further include a second die, the second die including second processing logic and a third connection from a secondary device coupled to the second processing logic. The secondary device is outside the system. The second processing logic is configured to select among three configurations based on signals from the second processing logic and the secondary device: sending first output data on the I/O output channel, sending second output data on the I/O output channel, or de-energizing the I/O channel.

Abstract: Apparatuses of systems that provide Safety Integration Levels (SILs) and Hardware Fault Tolerance (HFT) include a first die, the first die including first processing logic connected to a first connection and the first connection connected to second processing logic of a second die. The first die may further include a second connection to an input/output (I/O) channel where the second connection is coupled to the first processing logic. The apparatuses may further include a second die, the second die including second processing logic and a third connection from a secondary device coupled to the second processing logic. The secondary device is outside the system. The second processing logic is configured to select among three configurations based on signals from the second processing logic and the secondary device: sending first output data on the I/O output channel, sending second output data on the I/O output channel, or de-energizing the I/O channel.

Abstract: In a three-dimensional image generation apparatus, a CPU concatenates meshes of a plurality of objects which meet a predefined concatenation condition, and performs in advance vertex attribute transformation on the plurality of objects of which the meshes have been concatenated. The CPU regards as a single object, the plurality of objects on which the vertex attribute transformation has been performed, and transfers a rendering command, which instructs rendering of the plurality of objects regarded as the single object, to a GPU. The GPU renders, at a time, the plurality of objects that are regarded as the single object, upon receiving the rendering command from the CPU.

Abstract: In a three-dimensional image generation apparatus, a CPU concatenates meshes of a plurality of objects which meet a predefined concatenation condition, and performs in advance vertex attribute transformation on the plurality of objects of which the meshes have been concatenated. The CPU regards as a single object, the plurality of objects on which the vertex attribute transformation has been performed, and transfers a rendering command, which instructs rendering of the plurality of objects regarded as the single object, to a GPU. The GPU renders, at a time, the plurality of objects that are regarded as the single object, upon receiving the rendering command from the CPU.