Patents by Inventor Mattheus Heddes

Mattheus Heddes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Systems and methods for implementing error correcting code in a memory
    Patent number: 10061644
    Abstract: Systems and methods are disclosed for error correction control (ECC) for a memory device comprising a data portion and an ECC portion, the memory device coupled to a system on a chip (SoC). The SoC includes an ECC cache. On receipt of a request to write a line of data to the memory, a determination is made if the data is compressible. If so, the data line is compressed. ECC bits are generated for the compressed or uncompressed data line. A determination is made if an ECC cache line is associated with the received data line. If the data line is compressible, the ECC bits are appended to the compressed data line and the appended data line is stored in the data portion of the memory. Otherwise, the ECC bits are stored in the ECC cache and the data line is stored in the data portion of the memory.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: August 28, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Nhon Quach, Mainak Biswas, Pranjal Bhuyan, Jeffrey Shabel, Robert Hardacker, Rahul Gulati, Mattheus Heddes
  • SYSTEMS AND METHODS FOR IMPLEMENTING ERROR CORRECTING CODE IN A MEMORY
    Publication number: 20170123897
    Abstract: Systems and methods are disclosed for error correction control (ECC) for a memory device comprising a data portion and an ECC portion, the memory device coupled to a system on a chip (SoC). The SoC includes an ECC cache. On receipt of a request to write a line of data to the memory, a determination is made if the data is compressible. If so, the data line is compressed. ECC bits are generated for the compressed or uncompressed data line. A determination is made if an ECC cache line is associated with the received data line. If the data line is compressible, the ECC bits are appended to the compressed data line and the appended data line is stored in the data portion of the memory. Otherwise, the ECC bits are stored in the ECC cache and the data line is stored in the data portion of the memory.
    Type: Application
    Filed: January 12, 2016
    Publication date: May 4, 2017
    Inventors: Nhon Quach, Mainak Biswas, Pranjal Bhuyan, Jeffrey Shabel, Robert Hardacker, Rahul Gulati, Mattheus Heddes