Abstract: The present invention provides a method of fabricating a cathode requiring relatively few and somewhat simple steps. In one embodiment, a novel etchant gas chemistry dispenses with needing a second passivation layer. In one embodiment, a direct via is formed without a separate mask. In one embodiment, access and isolation features of a metallic gate are patterned in the same patterning operation as an associated passivation layer, dispensing with a need for separate patterning of each. In one embodiment, etching is effectuated with high selectivity for nitrides of silicon. In one embodiment, the requirement for at least one passivation layer deposition, a direct via masking step, and separate patterning steps for the passivation layer and metallic gate are eliminated. This effectively eliminates or substantially reduces associated costs, concomitantly reducing process completion time.

Abstract: A structure for a multilayer electrode. Specifically, in one embodiment, a multilayer electrode for a flat panel display device is disclosed. The multilayer electrode comprises a metal alloy layer and a protective layer. The metal alloy layer includes neodymium having a concentration of between greater than three atomic percent and six atomic percent. The protective layer is disposed above the metal alloy layer to form a multilayer stack. The multilayer stack is etched to form the multilayer electrode.

Abstract: An electrode structure for a display that includes lower electrodes and upper electrodes. In one embodiment, lower and upper electrodes are formed of either an aluminum alloy or a silver alloy. In another embodiment, upper and lower electrodes are formed using a metal alloy layer over which a cladding layer is deposited. A silicon nitride passivation layer is used to protect the upper electrodes from damage in subsequent process steps. Various other materials and structures are also disclosed that protect the upper electrodes from damage in subsequent process steps.

Abstract: An electron-emitting device (20, 70, 80, or 90) contains an electrode, either a control electrode (38) or an emitter electrode (32), having a specified portion situated off to the side of the bulk of the electrode. For a control electrode, the specified portion is an exposure portion (38EA or 38EB) having openings that expose electron-emissive elements (50A or 50B) situated over an emitter electrode. For an emitter electrode, the specified portion is an emitter-coupling portion situated below at least one electron-emissive element exposed through at least one opening in a control electrode. Configuring the device in this way enables the control-electrode-to-emitter-electrode capacitance to be quite small, thereby enhancing the device's switching speed. If the specified portion of the electrode becomes short circuited to the other electrode, the short-circuit defect can be removed by severing the specified portion from the remainder of its electrode.

Abstract: An electrode structure for a display that includes lower electrodes and upper electrodes. In one embodiment, lower and upper electrodes are formed of either an aluminum alloy or a silver alloy. In another embodiment, upper and lower electrodes are formed using a metal alloy layer over which a cladding layer is deposited. A silicon nitride passivation layer is used to protect the upper electrodes from damage in subsequent process steps. Various other materials and structures are also disclosed that protect the upper electrodes from damage in subsequent process steps.

Abstract: One embodiment of the present invention provides a method of fabricating a cathode requiring relatively few and somewhat simple steps. One embodiment also provides a method of fabricating a cathode which eliminates a direct via masking step. One embodiment provides a method of fabricating a cathode which reduces manufacturing costs and increases the efficiency and productivity of manufacturing lines engaged in cathode fabrication. One embodiment provides a method of fabricating a cathode, which reduces the unit cost of thin CRTs. In one embodiment, a novel method effectuates fabrication of a cathode by a process requiring relatively few and somewhat simpler steps. Importantly, in the present embodiment, the requirement for at least one conventionally required direct via masking steps is eliminated. This effectively eliminates or substantially reduces associated costs, concomitantly reducing process completion time.

Abstract: The present invention provides a method of fabricating a cathode requiring relatively few and somewhat simple steps. In one embodiment, a novel etchant gas chemistry dispenses with needing a second passivation layer. In one embodiment, a direct via is formed without a separate mask. In one embodiment, access and isolation features of a metallic gate are patterned in the same patterning operation as an associated passivation layer, dispensing with a need for separate patterning of each. In one embodiment, etching is effectuated with high selectivity for nitrides of silicon. In one embodiment, the requirement for at least one passivation layer deposition, a direct via masking step, and separate patterning steps for the passivation layer and metallic gate are eliminated. This effectively eliminates or substantially reduces associated costs, concomitantly reducing process completion time.

Abstract: One embodiment of the present invention provides a method of fabricating a cathode requiring relatively few and somewhat simple steps. One embodiment also provides a method of fabricating a cathode which eliminates a passivation layer masking step. One embodiment provides a method of fabricating a cathode which reduces manufacturing costs and increases the efficiency and productivity of manufacturing lines engaged in cathode fabrication. One embodiment provides a method of fabricating a cathode, which reduces the unit cost of thin CRTs. In one embodiment, a novel method effectuates fabrication of a cathode by a process requiring relatively few and somewhat simpler steps. Importantly, in the present embodiment, the requirement for at least one conventionally required passivation layer masking steps is eliminated. This effectively eliminates or substantially reduces associated costs, concomitantly reducing process completion time.

Abstract: An electron-emitting device (20, 70, 80, or 90) contains an electrode, either a control electrode (38) or an emitter electrode (32), having a specified portion situated off to the side of the bulk of the electrode. For a control electrode, the specified portion is an exposure portion (38EA or 38EB) having openings that expose electron-emissive elements (50A or 50B) situated over an emitter electrode. For an emitter electrode, the specified portion is an emitter-coupling portion situated below at least one electron-emissive element exposed through at least one opening in a control electrode. Configuring the device in this way enables the control-electrode-to-emitter-electrode capacitance to be quite small, thereby enhancing the device's switching speed. If the specified portion of the electrode becomes short circuited to the other electrode, the short-circuit defect can be removed by severing the specified portion from the remainder of its electrode.

Abstract: One embodiment of the present invention provides a method of fabricating a cathode requiring relatively few and somewhat simple steps. One embodiment also provides a method of fabricating a cathode which eliminates a passivation layer masking step. One embodiment provides a method of fabricating a cathode which reduces manufacturing costs and increases the efficiency and productivity of manufacturing lines engaged in cathode fabrication. One embodiment provides a method of fabricating a cathode, which reduces the unit cost of thin CRTs. In one embodiment, a novel method effectuates fabrication of a cathode by a process requiring relatively few and somewhat simpler steps. Importantly, in the present embodiment, the requirement for at least one conventionally required passivation layer masking steps is eliminated. This effectively eliminates or substantially reduces associated costs, concomitantly reducing process completion time.

Abstract: One embodiment of the present invention provides a method of fabricating a cathode requiring relatively few and somewhat simple steps. One embodiment also provides a method of fabricating a cathode which eliminates a direct via masking step. One embodiment provides a method of fabricating a cathode which reduces manufacturing costs and increases the efficiency and productivity of manufacturing lines engaged in cathode fabrication. One embodiment provides a method of fabricating a cathode, which reduces the unit cost of thin CRTs. In one embodiment, a novel method effectuates fabrication of a cathode by a process requiring relatively few and somewhat simpler steps. Importantly, in the present embodiment, the requirement for at least one conventionally required direct via masking steps is eliminated. This effectively eliminates or substantially reduces associated costs, concomitantly reducing process completion time.

Abstract: An improved method for planarizing an isolation slot, having its walls previously oxidized, is disclosed which comprises depositing a first layer of a material; etching the first layer back to a predetermined depth below a reference point; depositing a second layer of an oxidizable material on the surface of the first layer; etching the second layer; and then oxidizing the second layer of oxidizable material. Formulas are disclosed for calculating the minimum and maximum depths of the etch back of the second layer and the minimum depth of the etch back of the first layer given the width of the slot and the thickness of the oxide layer to be grown in the surface of the second layer to thereby insure that any voids, microcracks, or discontinuities formed in the second layer are removed by the etch and that the oxide subsequently grown in the surface of the second layer does not penetrate down to the surface of the first layer and any voids, microcracks, or discontinuities therein.

Abstract: An improved method is disclosed for isolating active devices in an integrated circuit structure containing both CMOS and bipolar devices to simultaneously form isolation regions to separate CMOS channels from adjacent channels or bipolar devices as well as to separate adjacent bipolar devices from one another. The improved method of isolation also results in the simultaneous formation of a retrograde p-well for the n-channel device. The improved method comprises implanting, into a substrate having field oxide portions previously grown thereon, impurities capable of forming one or more isolation regions, between the active devices, at an energy level sufficiently high to permit penetration of the impurities through the field oxide.