Abstract: A programmable analog tile integrated circuit is configured over a standardized bus by communicating tile configuration information from a first integrated circuit tile, through a second integrated circuit tile, to a third integrated circuit tile. Each of the three integrated circuit tiles is part of an integrated circuit. The standardized bus is formed when the tiles are placed adjacent one another. Data bus and control signal conductors of the adjacent tiles line up and interconnect such that each signal conductor is electrically connected to every tile. Tile configuration information may be written to a selected register identified by an address in any selected one of the tiles using the data bus and control lines, regardless of the relative physical locations of the tile sending and the tile receiving the information. Thus, tile configuration information may pass from one tile to another tile, through any number of intermediate tiles.

Abstract: A programmable analog tile integrated circuit is configured over a standardized bus by communicating tile configuration information from a first integrated circuit tile, through a second integrated circuit tile, to a third integrated circuit tile. Each of the three integrated circuit tiles is part of an integrated circuit. The standardized bus is formed when the tiles are placed adjacent one another. Data bus and control signal conductors of the adjacent tiles line up and interconnect such that each signal conductor is electrically connected to every tile. Tile configuration information may be written to a selected register identified by an address in any selected one of the tiles using the data bus and control lines, regardless of the relative physical locations of the tile sending and the tile receiving the information. Thus, tile configuration information may pass from one tile to another tile, through any number of intermediate tiles.

Abstract: A programmable analog tile integrated circuit is configured over a standardized bus by communicating tile configuration information from a first integrated circuit tile, through a second integrated circuit tile, to a third integrated circuit tile. Each of the three integrated circuit tiles is part of an integrated circuit. The standardized bus is formed when the tiles are placed adjacent one another. Data bus and control signal conductors of the adjacent tiles line up and interconnect such that each signal conductor is electrically connected to every tile. Tile configuration information may be written to a selected register identified by an address in any selected one of the tiles using the data bus and control lines, regardless of the relative physical locations of the tile sending and the tile receiving the information. Thus, tile configuration information may pass from one tile to another tile, through any number of intermediate tiles.

Abstract: A step-down (buck) switching regulator regulates output current without sensing a current external to a converter integrated circuit. The regulator generates a set current that is indicative of a predetermined current level to which the output current is regulated. The regulator generates a sense current whose magnitude is proportional to an inductor current flowing through a power switch during an on time. During a first time period, the sense current is less than the set current. During a second time period, the sense current is greater than the set current. The output current of the regulator is maintained at the predetermined current level such that the first time period is equal to the second time period when the output current equals the predetermined current level. The set current is compared to the sense current in circuitry inside a bootstrap power generator whose voltage fluctuates with the voltage across the inductor.

Abstract: A programmable analog tile integrated circuit configuration tool communicates a power management control characteristic query soliciting control requirement information for a novel Power Management Integrated Circuit (PMIC) tile in a Multi-Tile Power Management Integrated Circuit (MTPMIC). The configuration tool receives a user response to the query indicating control requirements across a network. The PMIC tile includes configuration registers. Configuration information bit values stored in the configuration registers control the operational characteristics of the functional circuitry of the tile. The configuration registers of each novel PMIC tile are accessible at pre-defined addresses on a standardized bus of the MTPMIC. In response to the user response, the configuration tool generates appropriate tile configuration information for loading the configuration registers such that the PMIC tile within the MTPMIC is programmed to satisfy the user's control requirements.

Abstract: A programmable analog tile integrated circuit placement tool allows a user to manipulate a graphical representation of a first power management integrated circuit (PMIC) tile with respect to a graphical representation of a second PMIC tile in a proposed Multi-Tile Power Management Integrated Circuit (MTPMIC). The novel PMIC tiles have pre-defined physical structures including a bus portion and a memory structure for storing configuration information for configuring the tile. When appropriately placed in a MTPMIC, the bus portions of the selected tiles automatically form a standardized bus that accommodates all signal communication required for a functioning MTPMIC. A remote user with minimal training in analog circuit design may command the placement of individual tiles in a proposed MTPMIC layout. Upon receiving a user response indicating satisfaction with the placement of PMIC tiles, the tool quickly and automatically generates physical layout data suitable for fabrication of the MTPMIC.

Abstract: A step-down (buck) switching regulator regulates output current without sensing a current external to a converter integrated circuit. The regulator generates a set current that is indicative of a predetermined current level to which the output current is regulated. The regulator generates a sense current whose magnitude is proportional to an inductor current flowing through a power switch during an on time. During a first time period, the sense current is less than the set current. During a second time period, the sense current is greater than the set current. The output current of the regulator is maintained at the predetermined current level such that the first time period is equal to the second time period when the output current equals the predetermined current level. The set current is compared to the sense current in circuitry inside a bootstrap power generator whose voltage fluctuates with the voltage across the inductor.

Abstract: An Analog Tile Selection, Placement, Configuration and Programming (ATSPCP) tool communicates a power management characteristic query over a network. The query is displayed to a user on a webpage. The query is a solicitation for desired characteristics of a Power Management Integrated Circuit (PMIC). After receiving user requirements in a response to the query, the tool selects a number of power management integrated circuit tiles having pre-defined physical structures. The pre-defined structure of each tile includes a bus portion and a memory structure for storing configuring information for the tile. When combined in a Multi-Tile Power Management Integrated Circuit (MTPMIC), the bus portions of the selected tiles automatically form a standardized bus that accommodates all signal communication required for a functioning MTPMIC that meets the user requirements. The ATSPCP tool combines the physical layout data of each selected PMIC tile to form composite physical layout data for the overall MTPMIC.

Abstract: A step-down (buck) switching regulator regulates output current without sensing a current external to a converter integrated circuit. The regulator generates a set current that is indicative of a predetermined current level to which the output current is regulated. The regulator generates a sense current whose magnitude is proportional to an inductor current flowing through a power switch during an on time. During a first time period, the sense current is less than the set current. During a second time period, the sense current is greater than the set current. The output current of the regulator is maintained at the predetermined current level such that the first time period is equal to the second time period when the output current equals the predetermined current level. The set current is compared to the sense current in circuitry inside a bootstrap power generator whose voltage fluctuates with the voltage across the inductor.

Abstract: An average current-mode controlled converter has a buck mode, a boost mode, and a four-switch mode. In one example, the converter operates in one of the three modes, depending on the difference between the converter output voltage VOUT and the converter input voltage VIN. Whether the four-switch mode is a full-time four-switch mode or a partial four-switch mode is user programmable. The novel converter can also be programmed to operate in other ways. For example, the converter can be programmed so that there is no intervening four-switch mode, but rather the converter operates either in a buck or a boost mode depending on VOUT-VIN. The converter can also be programmed so that the converter always operates in a conventional full-time four-switch mode. In one embodiment, the converter is programmed by setting an offset between two internally generated ramp signals and by setting associated limiting and inverting circuits.

Abstract: A programmable analog tile integrated circuit programming tool communicates a power management control characteristic query soliciting control requirement information for a novel power management integrated circuit (PMIC) tile in a multi-tile power management integrated circuit (MTPMIC). The programming tool receives a user response to the query indicating control requirements across a network. The novel PMIC tiles have a pre-defined physical structure including all memory structures required for configuration of each tile and a bus portion. When combined in a multi-tile power management integrated circuit (MTPMIC), the bus portions of the selected tiles automatically form a standardized bus that accommodates all signal communication required for a functioning MTPMIC. The memory structure of each tile is individually addressable via the standardized bus. Thus, in response to control requirements, the programming tool programs a PMIC tile that is part of a MTPMIC to meet the control requirements.

Abstract: A flyback AC/DC switching converter has a constant voltage (CV) mode. The CV mode has sub-modes. In one sub-mode (“mid output power sub-mode”), the output voltage (VOUT) of the converter is regulated using both pulse width modulation and pulse frequency modulation. Both types of modulation are used simultaneously. In a second sub-mode (“low output power sub-mode”), VOUT is regulated using pulse width modulation, but the converter switching frequency is fixed at a first frequency. By setting the first frequency at a frequency above the frequency limit of human hearing, an undesirable audible transformer humming that might otherwise occur is avoided. In some embodiments, the converter has a third sub-mode (“high output power sub-mode”), in which pulse width modulation is used but the switching frequency is fixed at a second frequency. By proper setting of the second frequency, undesirable EMI radiation and other problems that might otherwise occur are avoided.

Abstract: An integrated circuit includes a plurality of tiles. One tile is a master tile. Other tiles contain writable registers of memory structures. Information for configuring circuitry of the tile is stored in the register in the tile. An individual one of the registers can be written via the master tile. Each memory structure of a register includes a non-volatile floating gate cell (that stores the configuration information) as well as a volatile cell. All transistors have the same gate insulator thickness. Although a programming pulse signal is applied to all memory structures, the state of the non-volatile cell of a memory structure is only changed if the state stored by the associated non-volatile cell differs from the state stored by the volatile cell. Floating gates are automatically refreshed by the programming pulse signal. By storing configuration information in each tile, inefficiencies associated with using blocks of non-volatile memory are avoided.

Abstract: A flyback AC/DC switching converter has a constant voltage (CV) mode. The CV mode has sub-modes. In one sub-mode (“mid output power sub-mode”), the output voltage (VOUT) of the converter is regulated using both pulse width modulation and pulse frequency modulation. Both types of modulation are used simultaneously. In a second sub-mode (“low output power sub-mode”), VOUT is regulated using pulse width modulation, but the converter switching frequency is fixed at a first frequency. By setting the first frequency at a frequency above the frequency limit of human hearing, an undesirable audible transformer humming that might otherwise occur is avoided. In some embodiments, the converter has a third sub-mode (“high output power sub-mode”), in which pulse width modulation is used but the switching frequency is fixed at a second frequency. By proper setting of the second frequency, undesirable EMI radiation and other problems that might otherwise occur are avoided.

Abstract: A power converter having a switched capacitor buck/boost operation has first and second switches coupled to a first switching node, third and fourth switches coupled to a second switching node, a capacitor coupled between the first and second switching nodes, and an inductor coupled to the first switching node. A switch controller controls the switches to operate in voltage step-down mode and voltage step-up mode depending on a difference between converter output voltage VOUT and converter input voltage VIN. In a buck-optimized topology operating in a step-down mode, an output current flowing through the first switching node flows through only one switch at a given time. In a boost-optimized topology operating in a step-up mode, an output current flowing through the first switching node flows through only one switch at a given time. As a result, a more compact and efficient power converter may be realized at lower cost.

Abstract: A programmable analog tile integrated circuit programming tool communicates a power management control characteristic query soliciting control requirement information for a novel power management integrated circuit (PMIC) tile in a multi-tile power management integrated circuit (MTPMIC). The programming tool receives a user response to the query indicating control requirements across a network. The novel PMIC tiles have a pre-defined physical structure including all memory structures required for configuration of each tile and a bus portion. When combined in a multi-tile power management integrated circuit (MTPMIC), the bus portions of the selected tiles automatically form a standardized bus that accommodates all signal communication required for a functioning MTPMIC. The memory structure of each tile is individually addressable via the standardized bus. Thus, in response to control requirements, the programming tool programs a PMIC tile that is part of a MTPMIC to meet the control requirements.

Abstract: A programmable analog tile integrated circuit placement tool allows a user to manipulate a graphical representation of a first power management integrated circuit (PMIC) tile with respect to a graphical representation of a second PMIC tile in a proposed Multi-Tile Power Management Integrated Circuit (MTPMIC). The novel PMIC tiles have pre-defined physical structures including a bus portion and a memory structure for storing configuration information for configuring the tile. When appropriately placed in a MTPMIC, the bus portions of the selected tiles automatically form a standardized bus that accommodates all signal communication required for a functioning MTPMIC. A remote user with minimal training in analog circuit design may command the placement of individual tiles in a proposed MTPMIC layout. Upon receiving a user response indicating satisfaction with the placement of PMIC tiles, the tool quickly and automatically generates physical layout data suitable for fabrication of the MTPMIC.

Abstract: An Analog Tile Selection, Placement, Configuration and Programming (ATSPCP) tool communicates a power management characteristic query over a network. The query is displayed to a user on a webpage. The query is a solicitation for desired characteristics of a Power Management Integrated Circuit (PMIC). After receiving user requirements in a response to the query, the tool selects a number of power management integrated circuit tiles having pre-defined physical structures. The pre-defined structure of each tile includes a bus portion and a memory structure for storing configuring information for the tile. When combined in a Multi-Tile Power Management Integrated Circuit (MTPMIC), the bus portions of the selected tiles automatically form a standardized bus that accommodates all signal communication required for a functioning MTPMIC that meets the user requirements. The ATSPCP tool combines the physical layout data of each selected PMIC tile to form composite physical layout data for the overall MTPMIC.

Abstract: A programmable analog tile integrated circuit configuration tool communicates a power management control characteristic query soliciting control requirement information for a novel Power Management Integrated Circuit (PMIC) tile in a Multi-Tile Power Management Integrated Circuit (MTPMIC). The configuration tool receives a user response to the query indicating control requirements across a network. The PMIC tile includes configuration registers. Configuration information bit values stored in the configuration registers control the operational characteristics of the functional circuitry of the tile. The configuration registers of each novel PMIC tile are accessible at pre-defined addresses on a standardized bus of the MTPMIC. In response to the user response, the configuration tool generates appropriate tile configuration information for loading the configuration registers such that the PMIC tile within the MTPMIC is programmed to satisfy the user's control requirements.

Abstract: A programmable analog tile integrated circuit is configured over a standardized bus by communicating tile configuration information from a first integrated circuit tile, through a second integrated circuit tile, to a third integrated circuit tile. Each of the three integrated circuit tiles is part of an integrated circuit. The standardized bus is formed when the tiles are placed adjacent one another. Data bus and control signal conductors of the adjacent tiles line up and interconnect such that each signal conductor is electrically connected to every tile. Tile configuration information may be written to a selected register identified by an address in any selected one of the tiles using the data bus and control lines, regardless of the relative physical locations of the tile sending and the tile receiving the information. Thus, tile configuration information may pass from one tile to another tile, through any number of intermediate tiles.