Patents by Inventor Matthew A. Jared

Matthew A. Jared has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11960429
    Abstract: Methods, apparatus, and computer platforms and architectures employing many-to-many and many-to-one peripheral switches. The methods and apparatus may be implemented on computer platforms having multiple nodes, such as those employing a Non-uniform Memory Access (NUMA) architecture, wherein each node comprises a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a many-to-many peripheral switch that includes a plurality of downstream ports to which NICs and/or peripheral expansion slots are operatively coupled, or a many-to-one switch that enables a peripheral device to be shared by multiple nodes. During operation, packets are received at the NICs and DMA memory writes are initiated using memory write transactions identifying a destination memory address.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: April 16, 2024
    Assignee: Intel Corporation
    Inventors: Patrick Connor, Matthew A. Jared, Duke C. Hong, Elizabeth M. Kappler, Chris Pavlas, Scott P. Dubal
  • Publication number: 20230176987
    Abstract: Methods, apparatus, and computer platforms and architectures employing many-to-many and many-to-one peripheral switches. The methods and apparatus may be implemented on computer platforms having multiple nodes, such as those employing a Non-uniform Memory Access (NUMA) architecture, wherein each node comprises a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a many-to-many peripheral switch that includes a plurality of downstream ports to which NICs and/or peripheral expansion slots are operatively coupled, or a many-to-one switch that enables a peripheral device to be shared by multiple nodes. During operation, packets are received at the NICs and DMA memory writes are initiated using memory write transactions identifying a destination memory address.
    Type: Application
    Filed: December 15, 2022
    Publication date: June 8, 2023
    Inventors: Patrick Connor, Matthew A. JARED, Duke C. HONG, Elizabeth M. KAPPLER, Chris Pavlas, Scott P. Dubal
  • Patent number: 11593292
    Abstract: Methods, apparatus, and computer platforms and architectures employing many-to-many and many-to-one peripheral switches. The methods and apparatus may be implemented on computer platforms having multiple nodes, such as those employing a Non-uniform Memory Access (NUMA) architecture, wherein each node comprises a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a many-to-many peripheral switch that includes a plurality of downstream ports to which NICs and/or peripheral expansion slots are operatively coupled, or a many-to-one switch that enables a peripheral device to be shared by multiple nodes. During operation, packets are received at the NICs and DMA memory writes are initiated using memory write transactions identifying a destination memory address.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: February 28, 2023
    Assignee: Intel Corporation
    Inventors: Patrick Connor, Matthew A. Jared, Duke C. Hong, Elizabeth M. Kappler, Chris Pavlas, Scott P. Dubal
  • Publication number: 20200301864
    Abstract: Methods, apparatus, and computer platforms and architectures employing many-to-many and many-to-one peripheral switches. The methods and apparatus may be implemented on computer platforms having multiple nodes, such as those employing a Non-uniform Memory Access (NUMA) architecture, wherein each node comprises a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a many-to-many peripheral switch that includes a plurality of downstream ports to which NICs and/or peripheral expansion slots are operatively coupled, or a many-to-one switch that enables a peripheral device to be shared by multiple nodes. During operation, packets are received at the NICs and DMA memory writes are initiated using memory write transactions identifying a destination memory address.
    Type: Application
    Filed: June 5, 2020
    Publication date: September 24, 2020
    Applicant: INTEL CORPORATION
    Inventors: Patrick Connor, Matthew A. Jared, Duke C. Hong, Elizabeth M. Kappler, Chris Pavlas, Scott P. Dubal
  • Patent number: 10684973
    Abstract: Methods, apparatus, and computer platforms and architectures employing many-to-many and many-to-one peripheral switches. The methods and apparatus may be implemented on computer platforms having multiple nodes, such as those employing a Non-uniform Memory Access (NUMA) architecture, wherein each node comprises a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a many-to-many peripheral switch that includes a plurality of downstream ports to which NICs and/or peripheral expansion slots are operatively coupled, or a many-to-one switch that enables a peripheral device to be shared by multiple nodes. During operation, packets are received at the NICs and DMA memory writes are initiated using memory write transactions identifying a destination memory address.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Patrick Connor, Matthew A. Jared, Duke C. Hong, Elizabeth M. Kappler, Chris Pavlas, Scott P. Dubal
  • Publication number: 20180091447
    Abstract: Technologies for dynamically transitioning network traffic host buffers of a network computing device include the software abstraction of one or more hardware queues of the network computing device based on a network flow type associated with network traffic received by the network computing device. The network computing device is configured to identify a queue transition event, completing pending transactions in one or more of the software abstracted queues, and transition the abstracted queues to handle the flow type associated with the queue transition event.
    Type: Application
    Filed: September 23, 2016
    Publication date: March 29, 2018
    Inventors: Matthew A. Jared, Duke C. Hong, Manasi Deval
  • Patent number: 9471350
    Abstract: Methods, apparatus, software, and system architectures for supporting virtualized system migrations and scaling. Under aspects of a method, data is automatically collected and aggregated at multiple levels by a plurality of agents for each of multiple data centers. The data includes data relating to virtual machine utilization, data relating to electrical utilization costs, data relating to data center utilization, and data relating to triggers events. The data is processed to determine whether to migrate virtual servers from a first data center to a second data center. The software architecture includes a plurality of modules including a controller, data center profile, transition triggers, power cost profile, and virtual machine package module. The agents are implemented in an agent hierarchy and configured to collect data themselves and/or aggregate data from other agents and provide an API to facilitate access to collected data and agent services.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: October 18, 2016
    Assignee: Intel Corporation
    Inventors: Chris Pavlas, Duke C. Hong, Scott P. Dubal, Elizabeth M. Kappler, Patrick Connor, Matthew A. Jared
  • Patent number: 9047417
    Abstract: Methods, apparatus, and computer platforms and architectures employing node aware network interfaces are disclosed. The methods and apparatus may be implemented on computer platforms such as those employing a Non-uniform Memory Access (NUMA) architecture including a plurality of nodes, each node comprising a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a NUMA aware Network Interface Controller (NIC). Under one method, a packet is received from a network at a first NIC comprising a component of a first node, and a determination is made that packet data for the packet is to be forwarded to a second node including a second NIC. The packet data is then forwarded from the first NIC to the second NIC via a NIC-to-NIC interconnect link. Upon being received at the second NIC, processing of the packet (data) is handled as if the packet was received from the network at the second NIC.
    Type: Grant
    Filed: October 29, 2012
    Date of Patent: June 2, 2015
    Assignee: Intel Corporation
    Inventors: Patrick Conner, Chris Pavlas, Elizabeth M. Kappler, Matthew A. Jared, Duke C. Hong, Scott P. Dubal
  • Publication number: 20150088586
    Abstract: Methods, apparatus, software, and system architectures for supporting virtualized system migrations and scaling. Under aspects of a method, data is automatically collected and aggregated at multiple levels by a plurality of agents for each of multiple data centers. The data includes data relating to virtual machine utilization, data relating to electrical utilization costs, data relating to data center utilization, and data relating to triggers events. The data is processed to determine whether to migrate virtual servers from a first data center to a second data center. The software architecture includes a plurality of modules including a controller, data center profile, transition triggers, power cost profile, and virtual machine package module. The agents are implemented in an agent hierarchy and configured to collect data themselves and/or aggregate data from other agents and provide an API to facilitate access to collected data and agent services.
    Type: Application
    Filed: September 26, 2013
    Publication date: March 26, 2015
    Inventors: Chris Pavlas, Duke C. Hong, Scott P. Dubal, Elizabeth M. Kappler, Patrick Connor, Matthew A. Jared
  • Patent number: 8977784
    Abstract: An embodiment may include circuitry to be comprised at least in part in a first host, and at least one process to be executed, at least in part, by the circuitry. The circuitry may comprise a first port and a second port. The at least one process may detect, at least in part, a first bandwidth condition of the first port, and may associate, at least in part, in response at least in part to the first bandwidth condition, the first port and the second port with a port team. The second port may have been, prior to being associated, at least in part, with the port team, in a relatively lower power state compared to a relatively higher power state. The second port may be in the relatively higher power state after the second port is associated, at least in part, with the port team.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: March 10, 2015
    Assignee: Intel Corporation
    Inventors: Matthew A. Jared, Patrick Connor
  • Publication number: 20150067229
    Abstract: Methods, apparatus, and computer platforms and architectures employing many-to-many and many-to-one peripheral switches. The methods and apparatus may be implemented on computer platforms having multiple nodes, such as those employing a Non-uniform Memory Access (NUMA) architecture, wherein each node comprises a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a many-to-many peripheral switch that includes a plurality of downstream ports to which NICs and/or peripheral expansion slots are operatively coupled, or a many-to-one switch that enables a peripheral device to be shared by multiple nodes. During operation, packets are received at the NICs and DMA memory writes are initiated using memory write transactions identifying a destination memory address.
    Type: Application
    Filed: August 30, 2013
    Publication date: March 5, 2015
    Inventors: Patrick Connor, Matthew A. Jared, Duke C. Hong, Elizabeth M. Kappler, Chris Pavlas, Scott P. Dubal
  • Publication number: 20140122634
    Abstract: Methods, apparatus, and computer platforms and architectures employing node aware network interfaces are disclosed. The methods and apparatus may be implemented on computer platforms such as those employing a Non-uniform Memory Access (NUMA) architecture including a plurality of nodes, each node comprising a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a NUMA aware Network Interface Controller (NIC). Under one method, a packet is received from a network at a first NIC comprising a component of a first node, and a determination is made that packet data for the packet is to be forwarded to a second node including a second NIC. The packet data is then forwarded from the first NIC to the second NIC via a NIC-to-NIC interconnect link. Upon being received at the second NIC, processing of the packet (data) is handled as if the packet was received from the network at the second NIC.
    Type: Application
    Filed: October 29, 2012
    Publication date: May 1, 2014
    Inventors: Patrick Conner, Chris Pavlas, Elizabeth M. Kappler, Matthew A. Jared, Duke C. Hong, Scott P. Dubal
  • Patent number: 8621096
    Abstract: In an embodiment, a method is provided that may include generating, at least in part, at least one packet. The at least one packet may include an indication that the at least one packet comprises a control protocol packet. The at least one packet also may include, at least in part, an identification, at least in part, of at least one characteristic of at least one storage device, and/or the at least one packet may indicate, at least in part, a request for the identification. The at least one storage device may be associated, at least in part, with at least one network server. The identification may be generated, at least in part, in response, at least in part, to the request for the identification. Of course, many alternatives, modifications, and variations are possible without departing from this embodiment.
    Type: Grant
    Filed: April 15, 2008
    Date of Patent: December 31, 2013
    Assignee: Intel Corporation
    Inventor: Matthew A. Jared
  • Publication number: 20110268111
    Abstract: An embodiment may include circuitry to be comprised at least in part in a first host, and at least one process to be executed, at least in part, by the circuitry. The circuitry may comprise a first port and a second port. The at least one process may detect, at least in part, a first bandwidth condition of the first port, and may associate, at least in part, in response at least in part to the first bandwidth condition, the first port and the second port with a port team. The second port may have been, prior to being associated, at least in part, with the port team, in a relatively lower power state compared to a relatively higher power state. The second port may be in the relatively higher power state after the second port is associated, at least in part, with the port team.
    Type: Application
    Filed: April 30, 2010
    Publication date: November 3, 2011
    Inventors: Matthew A. Jared, Patrick Connor
  • Publication number: 20090259760
    Abstract: In an embodiment, a method is provided that may include generating, at least in part, at least one packet. The at least one packet may include an indication that the at least one packet comprises a control protocol packet. The at least one packet also may include, at least in part, an identification, at least in part, of at least one characteristic of at least one storage device, and/or the at least one packet may indicate, at least in part, a request for the identification. The at least one storage device may be associated, at least in part, with at least one network server. The identification may be generated, at least in part, in response, at least in part, to the request for the identification. Of course, many alternatives, modifications, and variations are possible without departing from this embodiment.
    Type: Application
    Filed: April 15, 2008
    Publication date: October 15, 2009
    Inventor: Matthew A. Jared
  • Publication number: 20080077650
    Abstract: A method and apparatus is provided for transferring data between a device accessible via a home network and a storage system. The storage system advertises storage services to the device over the home network. The device issues a request to the storage service to download the data to the storage system by transmitting the data to the storage system over the home network using a storage protocol.
    Type: Application
    Filed: August 29, 2006
    Publication date: March 27, 2008
    Inventor: Matthew A. Jared