Abstract: Embodiments may provide a radiation hardened 10BASE-T Ethernet interface circuit suitable for space flight and in compliance with the IEEE 802.3 standard for Ethernet. The various embodiments may provide a 10BASE-T Ethernet interface circuit, comprising a field programmable gate array (FPGA), a transmitter circuit connected to the FPGA, a receiver circuit connected to the FPGA, and a transformer connected to the transmitter circuit and the receiver circuit. In the various embodiments, the FPGA, transmitter circuit, receiver circuit, and transformer may be radiation hardened.

Abstract: Embodiments may provide a radiation hardened 10BASE-T Ethernet interface circuit suitable for space flight and in compliance with the IEEE 802.3 standard for Ethernet. The various embodiments may provide a 10BASE-T Ethernet interface circuit, comprising a field programmable gate array (FPGA), a transmitter circuit connected to the FPGA, a receiver circuit connected to the FPGA, and a transformer connected to the transmitter circuit and the receiver circuit. In the various embodiments, the FPGA, transmitter circuit, receiver circuit, and transformer may be radiation hardened.

Abstract: A system is disclosed for remotely determining 6 degree of freedom of an object. Four or more radiating beacons are placed on an object, the beacons each simultaneously radiating a synchronized repeating code, the code being different for each beacon. A position sensor, such as a quadrant detector, receives the light signals from the beacons, and correlates the received beacon signals against the same signal sequences produced in the receiver. With orientation of the beacons on the object being known, and orientation of the quadrant detector, or receiver, being known, roll, pitch, yaw, and X, Y and Z position in a coordinate space of the object can be determined.

Abstract: A real time digital correlation system is disclosed. Reference filters are constructed to define a region of filter space, and filters may be predictively selected based on a trajectory of selected filters through the filter space. In some instances, selected features of a spacecraft are selected for correlation to produce full 6DoF information. In other instances, portions of a correlation target are selected for correlation to produce 6DoF information. Digital filters of the invention are preferably 4-bit filters, and use unique mapping algorithms to map phase and intensity information from larger images, such as 12, 16, 32 and 64 bit images, to the 4-bit format.

Abstract: A communication system for transmitting (T1) digital communication signals between a transmit site and a receiver site includes an M:1 multiplexer, coupled to a rate 1/N convolutional encoder, which is operative to output an encoded output signal modulated in quaternary phase shift keyed (QPSK) space having a prescribed symbol rate. The receive site has a rate 1/N Viterbi decoder which is operative to decode the encoded output signal output by the rate 1/N convolutional encoder, and a 1:M demultiplexer having an input coupled to the Viterbi decoder and M plurality of outputs, and being operative to demultiplex the decoded signal from the Viterbi decoder into a plurality of M time division multiplexed digital communication signals. For any selected values for of M and N, the product of M and N is constant.

Abstract: A clock regeneration scheme for a digital communication receiver has a first-in, first-out (FIFO) storage buffer into which received data is clocked in accordance with an input clock signal and a data valid signal. A fixed fractional delay line is coupled to provide respectively different phase delayed versions of the input clock signal and feeds a multiplexer that is controllably operative to couple one of the outputs of the fixed fractional delay line to a regenerated clock output port. A control loop, which includes the FIFO storage buffer, the output port and a steering control input of the multiplexer circuit, is operative to selectively change which output of the fixed fractional delay line is coupled by the multiplexer to the output port, so as to controllably cause the output clock signal to track the effective frequency of the valid data signal.

Abstract: A communication system for transmitting (T1) digital communication signals between a transmit site and a receiver site includes an M:1 multiplexer, coupled to a rate 1/N convolutional encoder, which is operative to output an encoded output signal modulated in quaternary phase shift keyed (QPSK) space having a prescribed symbol rate. The receive site has a rate 1/N Viterbi decoder which is operative to decode the encoded output signal output by the rate 1/N convolutional encoder, and a 1:M demultiplexer having an input coupled to the Viterbi decoder and M plurality of outputs, and being operative to demultiplex the decoded signal from the Viterbi decoder into a plurality of M time division multiplexed digital communication signals. For any selected values for of M and N, the product of M and N is constant.

Abstract: A measure is derived of the potential alignment of radio antennas associated with wireless transceivers, that are interfaced with terrestrial communication links transporting digital communication signals between geographically spaced apart transceiver sites. At a first radio site, a received signal strength indication is derived for signals sourced from a second radio site geographically remote with respect to the first site. In addition, received signal quality is measured on signals sourced from the second site. A measure of how well a first radio antenna at the first site is aimed in the direction of a second radio at the second site is derived in accordance with the received signal strength indication and the received signal quality measurement.

Abstract: A clock recovery scheme for a digital communication receiver has a fixed fractional delay line that is driven by a fixed frequency reference clock source, to provide a plurality of respectively offset phase delayed versions of the reference clock. A phase lock loop, to which the received signal is coupled, controllably steps through the phase delayed versions of the reference clock, so as to controllably increase or decrease the effective frequency of the reference clock and thereby produce a recovered clock signal.

Abstract: A clock regeneration scheme for a digital communication receiver has a first-in, first-out (FIFO) storage buffer into which received data is clocked in accordance with an input clock signal and a data valid signal. A fixed fractional delay line is coupled to provide respectively different phase delayed versions of the input clock signal and feeds a multiplexer that is controllably operative to couple one of the outputs of the fixed fractional delay line to a regenerated clock output port. A control loop, which includes the FIFO storage buffer, the output port and a steering control input of the multiplexer circuit, is operative to selectively change which output of the fixed fractional delay line is coupled by the multiplexer to the output port, so as to controllably cause the output clock signal to track the effective frequency of the valid data signal.

Abstract: A system for protecting configuration data of a programmable execution unit (PEU) comprises a programmable array and programming logic. The programming logic is configured to receive configuration data and to program the programmable array, based on the configuration data, such that the programmable array comprises functional logic and activation logic. The activation logic is configured to enable the functional logic upon detection of an activation key.

Abstract: A system for recovering a payload data stream from a framing data stream utilizes a buffer, a first counter, a second counter, and a clock synchronization element. The buffer is configured to receive the framing data stream and to store payload bits of the framing data stream. The buffer is further configured to transmit the payload bits based on a clock signal. The first counter is configured to produce a first value and to update the first value for each of the payload bits stored in the buffer. The second counter is configured to produce a second value and to update the second value based on the clock signal. The clock synchronization element is coupled to the first and second counters. The clock synchronization element is configured to compare the first and second values and to control a frequency of the clock signal based on comparisons of the first and second values.