Patents by Inventor Matthew A. Mertens
Matthew A. Mertens has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240012735Abstract: In an embodiment, a processor for redirecting requests includes a processing engine to execute a guest system, and monitoring circuitry coupled to the processing engine. The monitoring circuitry may be to: receive, from the guest system, a first request to access a first virtual counter; in response to a receipt of the first request, determine, based a mapping register of the processor, a first physical counter mapped to the first virtual counter; and redirect the first request to the first physical counter mapped to the first virtual counter. Other embodiments are described and claimed.Type: ApplicationFiled: December 24, 2020Publication date: January 11, 2024Inventors: Wei Wang, Matthew Merten, Beeman Strong, Andreas Kleen, Kan Liang, Gilbert Neiger, Kun Tian, Like Xu
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Publication number: 20230365228Abstract: A pontoon boat has a planing panel located between pontoons and configured such that a substantial portion of the planing panel planes or rides on top of the water while the boat is traveling at planing speeds, thus reducing friction and increasing efficiency and maneuverability. The boat may be a “tritoon” boat having three laterally spaced pontoons, in which case at least two planing panels are provided in the spaces or gaps between each pair of adjacent pontoons. Each planing panel may be segmented from front to rear, with the rear segment(s) being higher than the front segment to enhance the ability of the bow of the boat to ride out of the water while preventing water from impinging against the rear of the boat's underdeck. An inclined panel may be provided in front of the planing panel to reduce wave impact energy.Type: ApplicationFiled: May 12, 2023Publication date: November 16, 2023Inventors: Timothy Merten, Matthew Merten, Gerard Pettefer
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Publication number: 20230315470Abstract: Techniques and mechanisms for configuring processor event-based sampling (PEBS) with a set of control registers. In an embodiment, a first control register of a processor is programmed to store a physical address of a location in a buffer which receives PEBS records. The first control register is further programmed or otherwise configured to store an indication of a size of the buffer. A second control register of the processor stores a physical address of a location in the buffer were a next PEBS record is to be stored. In another embodiment, the processor further comprises multiple control registers which variously configure PEBS generation on a per-counter basis.Type: ApplicationFiled: March 30, 2022Publication date: October 5, 2023Applicant: Intel CorporationInventors: Matthew Merten, Beeman Strong, Moshe Cohen, Ahmad Yasin, Andreas Kleen, Stanislav Bratanov, Karthik Gopalakrishnan, Angela Schmid, Grant Zhou
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Patent number: 11586238Abstract: A clock generator includes an input coupled to receive an input clock signal from a first clock source, and a noise rejection circuit configured to provide an output clock signal based on the input clock signal. The noise rejection circuit includes an event generator having a digital counter circuit. The event generator is configured to generate a first event signal based on a count value of the digital counter circuit, in which the noise rejection circuit is configured to produce an edge on the output clock signal in response to both the event signal and a state of the input clock signal.Type: GrantFiled: December 15, 2021Date of Patent: February 21, 2023Assignee: NXP B.V.Inventors: Robert Matthew Mertens, Ateet Omer, Sanjay Kumar Wadhwa, Charles Eric Seaberg
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Patent number: 11223343Abstract: A noise suppression circuit includes a resistor-capacitor (RC) filter where a resistive element of the RC filter has a first terminal configured to receive an input data stream and a second terminal coupled to a circuit node Vrc and a capacitive element coupled to the circuit node, a logic gate having an input coupled to the circuit node and an output configured to provide a filtered data stream, and a switch. The switch is configured to short out the resistive element of the RC filter when the input data stream and the filtered data stream are at a same value and not short out the resistive element when the input data stream and the filtered data stream are at different values.Type: GrantFiled: April 14, 2020Date of Patent: January 11, 2022Assignee: NXP USA, Inc.Inventor: Robert Matthew Mertens
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Publication number: 20210320647Abstract: A noise suppression circuit includes a resistor-capacitor (RC) filter where a resistive element of the RC filter has a first terminal configured to receive an input data stream and a second terminal coupled to a circuit node Vrc and a capacitive element coupled to the circuit node, a logic gate having an input coupled to the circuit node and an output configured to provide a filtered data stream, and a switch. The switch is configured to short out the resistive element of the RC filter when the input data stream and the filtered data stream are at a same value and not short out the resistive element when the input data stream and the filtered data stream are at different values.Type: ApplicationFiled: April 14, 2020Publication date: October 14, 2021Inventor: Robert Matthew Mertens
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Patent number: 10972096Abstract: An electronic switch that includes a signal path with a first terminal side of the signal path including cascoded transistors in the signal path. When the switch is in an off state, the gate of one of the cascoded transistors is biased at an intermediate voltage different from the voltage applied to the gate of the other of the cascoded transistors. In one embodiment, having the gate of one of the cascoded transistors biased at an intermediate voltage in an off state may reduce leakage current into a signal terminal of the switch. The electronic switch includes an injection shunting device (e.g. such as a transistor) connected to a node of the signal path. In one embodiment, the injection shunting device prevents the voltage of the node from reaching a specific voltage level due to leakage current when the switch is in an off state.Type: GrantFiled: June 28, 2019Date of Patent: April 6, 2021Assignee: NXP USA, INC.Inventors: Robert Matthew Mertens, James Robert Feddeler, Michael A. Stockinger
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Patent number: 10956160Abstract: A processor and method are described for a multi-level reservation station.Type: GrantFiled: March 27, 2019Date of Patent: March 23, 2021Assignee: Intel CorporationInventors: Mark Dechene, Srikanth Srinivasan, Matthew Merten, Ammon Christiansen
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Patent number: 10906146Abstract: A zero clamp force fixture assembly may comprise a body comprising a locating surface and a side, a neck extending away from the side of the body, a zero force clamp coupled to the neck, and a universal locating feature coupled to the locating surface. The neck may taper towards an interface with the zero force clamp. The zero force clamp may comprise an upper jaw and a lower jaw.Type: GrantFiled: June 22, 2018Date of Patent: February 2, 2021Assignee: Raytheon Technologies CorporationInventors: Matthew A. Mertens, Gordon Miller Reed
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Publication number: 20200412363Abstract: An electronic switch that includes a signal path with a first terminal side of the signal path including cascoded transistors in the signal path. When the switch is in an off state, the gate of one of the cascoded transistors is biased at an intermediate voltage different from the voltage applied to the gate of the other of the cascoded transistors. In one embodiment, having the gate of one of the cascoded transistors biased at an intermediate voltage in an off state may reduce leakage current into a signal terminal of the switch. The electronic switch includes an injection shunting device (e.g. such as a transistor) connected to a node of the signal path. In one embodiment, the injection shunting device prevents the voltage of the node from reaching a specific voltage level due to leakage current when the switch is in an off state.Type: ApplicationFiled: June 28, 2019Publication date: December 31, 2020Inventors: Robert Matthew Mertens, James Robert Feddeler, Michael A. Stockinger
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Publication number: 20200310801Abstract: A processor and method are described for a multi-level reservation station.Type: ApplicationFiled: March 27, 2019Publication date: October 1, 2020Inventors: Mark Dechene, Srikanth Srinivasan, Matthew Merten, Ammon Christiansen
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Patent number: 10710272Abstract: A monolithic airflow testing mold suitable for mating with a workpiece includes a platform portion formed from a first material having a first hardness. The mold further includes a workpiece mating portion surrounding by the platform portion. The mating portion includes a support region abutting the platform portion and formed from a second material having a second hardness, and a sealing surface positioned above the support region and formed from a third material having a third hardness. The sealing surface is configured to mate with and extend into a hollow portion of the workpiece. The first hardness is different from at least one of the second and third hardnesses.Type: GrantFiled: December 14, 2017Date of Patent: July 14, 2020Assignee: United Technologies CorporationInventors: Mary Lynn Tall, Matthew A. Mertens
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Patent number: 10659038Abstract: A method of powering up a circuit includes powering up a latch circuit in a known latch state by applying a first power supply voltage differential of a first voltage domain across power supply terminals of the latch circuit. A current diode inhibits current diode in a current path between a latch node of the latch circuit and a power supply terminal when the power supply voltage differential is below a threshold voltage during the powering up in which the inhibiting prevents the latch circuit from switching from the known latch state during the powering up.Type: GrantFiled: March 12, 2019Date of Patent: May 19, 2020Assignee: NXP USA, Inc.Inventors: Robert Matthew Mertens, James Robert Feddeler, Stefano Pietri
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Publication number: 20190389018Abstract: A zero clamp force fixture assembly may comprise a body comprising a locating surface and a side, a neck extending away from the side of the body, a zero force clamp coupled to the neck, and a universal locating feature coupled to the locating surface. The neck may taper towards an interface with the zero force clamp. The zero force clamp may comprise an upper jaw and a lower jaw.Type: ApplicationFiled: June 22, 2018Publication date: December 26, 2019Applicant: UNITED TECHNOLOGIES CORPORATIONInventors: Matthew A. Mertens, Gordon Miller Reed
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Patent number: 10409612Abstract: An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a data conflict, a speculative timer expiration, a disallowed instruction attribute or type, etc. And hardware, firmware, software, or a combination thereof makes an abort determination based on the tracked abort events. As an example, hardware may make an initial abort determination based on one or more predefined events or choose to pass the event information up to a firmware or software handler to make such an abort determination. Upon determining an abort of a speculative code region is to be performed, hardware, firmware, software, or a combination thereof performs the abort, which may include following a fallback path specified by hardware or software.Type: GrantFiled: December 26, 2015Date of Patent: September 10, 2019Assignee: Intel CorporationInventors: Martin G. Dixon, Ravi Rajwar, Konrad K. Lai, Robert S. Chappell, Rajesh S. Parthasarathy, Alexandre J. Farcy, Ilhyun Kim, Prakash Math, Matthew Merten, Vijaykumar Kadgi
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Patent number: 10409611Abstract: An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a data conflict, a speculative timer expiration, a disallowed instruction attribute or type, etc. And hardware, firmware, software, or a combination thereof makes an abort determination based on the tracked abort events. As an example, hardware may make an initial abort determination based on one or more predefined events or choose to pass the event information up to a firmware or software handler to make such an abort determination. Upon determining an abort of a speculative code region is to be performed, hardware, firmware, software, or a combination thereof performs the abort, which may include following a fallback path specified by hardware or software.Type: GrantFiled: December 26, 2015Date of Patent: September 10, 2019Assignee: Intel CorporationInventors: Martin G. Dixon, Ravi Rajwar, Konrad K. Lai, Robert S. Chappell, Rajesh S. Parthasarathy, Alexandre J. Farcy, Ilhyun Kim, Prakash Math, Matthew Merten, Vijaykumar Kadgi
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Patent number: 10354991Abstract: An integrated circuit with protection against transient electrical stress events includes a trigger circuit having a first detection circuit coupled to a first supply voltage, a second detection circuit coupled to a second supply voltage, and a rail clamp device. During a first type of electrical stress event, the rail clamp device is activated in response to a first output signal provided by the first detection circuit. During a second type of electrical stress event, the rail clamp device is activated in response to a second output signal provided by the second detection circuit.Type: GrantFiled: August 7, 2018Date of Patent: July 16, 2019Assignee: NXP USA, Inc.Inventors: Robert Matthew Mertens, Michael A. Stockinger, Alexander Paul Gerdemann
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Patent number: 10331452Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for tracking the mode of processing devices in an instruction tracing system. The method may include receiving an indication of a change in a current execution mode of the processing device. The method may also include determining that the current execution mode of the received indication is different than a value of an execution mode of a first execution mode (EM) packet previously-generated by the IT module. The method may also include generating, based on the determining that the current execution mode is different, a second EM packet that provides a value of the current execution mode of the processing device to indicate the change in the execution mode for an instruction in a trace generated by the IT module. The method may further include generating transactional memory (TMX) packets having n bit mode pattern in the packet log. The n is at least two and the n bit mode indicates transaction status of the TMX operation.Type: GrantFiled: June 27, 2013Date of Patent: June 25, 2019Assignee: Intel CorporationInventors: Thilo Schmitt, Peter Lachner, Beeman Strong, Ofer Levy, Thomas Toll, Matthew Merten, Tong Li, Ravi Rajwar, Konrad Lai
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Publication number: 20190184600Abstract: A monolithic airflow testing mold suitable for mating with a workpiece includes a platform portion formed from a first material having a first hardness. The mold further includes a workpiece mating portion surrounding by the platform portion. The mating portion includes a support region abutting the platform portion and formed from a second material having a second hardness, and a sealing surface positioned above the support region and formed from a third material having a third hardness. The sealing surface is configured to mate with and extend into a hollow portion of the workpiece. The first hardness is different from at least one of the second and third hardnesses.Type: ApplicationFiled: December 14, 2017Publication date: June 20, 2019Inventors: Mary Lynn Tall, Matthew A. Mertens
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Patent number: 10320185Abstract: An integrated circuit for protecting against transient electrical stress events includes a rail clamp device, and a trigger circuit including a resistive-capacitive (RC) filter, a drive circuit including a first inverter stage receiving an input signal from the RC filter, the drive circuit is configured to enable the rail clamp device during a transient electrical stress event, and a stress event detection circuit coupled to the RC filter. The drive circuit includes a configurable activation voltage which is controlled by the stress event detection circuit, wherein the activation voltage is reduced when the transient electrical stress event is detected.Type: GrantFiled: September 22, 2016Date of Patent: June 11, 2019Assignee: NXP USA, Inc.Inventors: Robert Matthew Mertens, Alexander Paul Gerdemann, Michael A. Stockinger