Abstract: In a communication system that utilizes DMT technology to couple a primary site (102) to a plurality of secondary sites (104-108), the primary site (102) and each of the secondary sites (104-108) includes a DMT transmitter. Such a DMT transmitter includes a discrete multi-tone encoder that receives an ordered data stream and produces an encoded data stream based on bit loading information, and a data formatter operably coupled to the discrete multi-tone encoder, wherein the data formatter receives transmit data entries and produces the ordered data stream based on carrier channel allocation information.

Abstract: In a communication system that utilizes DMT technology to couple a primary site (102) to a plurality of secondary sites (104-108), the primary site (102) and each of the secondary sites (104-108) includes a DMT receiver. Such a DMT receiver includes a discrete multi-tone decoder that receives a time domain discrete multi-tone symbol and produces an ordered data stream based on bit loading information and a data de-formatter, operably coupled to the discrete multi-tone decoder, wherein the data de-formatter receives the ordered data stream and produces a recovered data stream based on carrier channel allocation information.

Abstract: In a communication system utilizing DMT technology to couple a primary site (102) to a plurality of secondary sites (104-108), infrastructure control channels are established in the following manner. Having obtained a plurality of site bit loading tables, the primary site (102) generates a control channel bit loading table from the plurality of site bit loading tables. From the control channel bit loading table, the primary site selects at least one carrier channel to function as the control channel. The selection is based on bandwidth requirements for the control channel.

Abstract: In a communication system that utilizes DMT technology to couple a primary site (102) to a plurality of secondary sites (104-108), carrier channel allocations may be updated as follows. At periodic intervals, the primary site requests updating bit loading information from the secondary sites. Upon receiving the updated bit loading information, the primary site (102) determines an updated call bit loading table for each active call. From this, the primary site (102) determines whether current carrier channel allocation provides sufficient bandwidth. When the current carrier channel allocation does not provide the sufficient bandwidth, the primary site modifies the current carrier channel allocation to meet the bandwidth requirements.

Abstract: In a communication system that utilizes DMT technology to couple a primary site (102) to a plurality of secondary sites (104-108), carrier channel allocations may be performed as follows. When a call request is received, the primary site (102) determines the number of required bits based on the bandwidth requirements of the call. Next, the primary site (102) determines whether the maximum bit loading of a given carrier channel exceeds the number of required bits. If yes, the primary site allocates a carrier channel having a bit loading that most closely matches the number of required bits. If no, the primary site allocates the carrier channel having the maximum bit loading to the call, then calculates a remaining number of required bits. From here, the primary site repeats the above process until a sufficient number of carrier channels have been allocated to the call.

Abstract: A phase locked loop (PLL) (40) simultaneously has both relatively-low power consumption and relatively-low jitter on a clock output signal. The PLL (40) includes a phase detector (41) and a phase error accumulator (42) connected to the output of the phase detector (41). The phase error accumulator (42) samples an output of the phase detector (41) at a relatively-high clock rate, but accumulates these samples and provides an output thereof to a loop filter (43) at a relatively-low clock rate. Thus the PLL (40) captures short periods of phase delay to maintain low clock output signal jitter, while at the same time, however, the loop filter (43) need only adjust its output periodically, at the relatively-low rate, thereby saving power. The phase detector (41) detects a metastable condition on a phase detector latch (60) and resolves to an up pulse or a down pulse to further reduce clock output signal jitter.