Patents by Inventor Matthew A. Thompson
Matthew A. Thompson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12173988Abstract: Disclosed is an extended range multi-caliber in-bore laser boresight system for sighting in a firearm. The device includes one or more hollow cartridge cases that resemble a standard firearm case lacking a bullet, a laser module, and an external electronic package. The laser module fits within the hollow cartridge case and is positioned within a firearm chamber. The laser exits the hollow cartridge through the firearm barrel to aid with zeroing a firearm sighting system. The laser diode is powerful enough to be visible at extended ranges in bright sunlight. The inventive boresight system can be used for zeroing any desired caliber, such as from 5.56 NATO to .50 BMG at extended range.Type: GrantFiled: April 5, 2023Date of Patent: December 24, 2024Assignee: The United States of America, Represented by the Secretary of the NavyInventors: Brandon W Rudolph, Matthew A Thompson, Daniel S Spoor
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Patent number: 12092484Abstract: A probe assembly for a tank includes a probe having a shaft with a proximal end and a distal end, and further includes an enlarged head at the distal end. A seal is formed from a plastic material and is mounted about the shaft adjacent the enlarged head. The seal has a hollow cylindrical body with a distal end and a proximal end, and further has a flange extending radially outward at the proximal end of the hollow cylindrical body spaced from the enlarged head. The cylindrical body has a uniform wall thickness extending from the proximal end to the flange.Type: GrantFiled: February 8, 2024Date of Patent: September 17, 2024Assignee: Peak Plastics, LLCInventor: Matthew A. Thompson
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Publication number: 20240280192Abstract: A conduit seal assembly for a wall opening in a wall includes a seal with an annular body. The annular body has a first end and a second opposed end, with the first end forming a conduit receiving end, and the second opposed end forming a seal insertion end. The seal insertion end has an outer diameter sized approximately equal to the wall opening in the wall into which the seal is to be inserted. The annular body further includes an outer lip between the conduit receiving end and the seal insertion end and additionally includes a tapered inner diameter that tapers to a smaller diameter at the seal insertion end so that when a conduit is inserted into the seal the conduit will cause the seal insertion end to expand to trap the seal in the wall at the wall opening.Type: ApplicationFiled: February 8, 2024Publication date: August 22, 2024Inventor: Matthew A. Thompson
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Publication number: 20230324142Abstract: Disclosed is an extended range multi-caliber in-bore laser boresight system for sighting in a firearm. The device includes one or more hollow cartridge cases that resemble a standard firearm case lacking a bullet, a laser module, and an external electronic package. The laser module fits within the hollow cartridge case and is positioned within a firearm chamber. The laser exits the hollow cartridge through the firearm barrel to aid with zeroing a firearm sighting system. The laser diode is powerful enough to be visible at extended ranges in bright sunlight. The inventive boresight system can be used for zeroing any desired caliber, such as from 5.56 NATO to .50 BMG at extended range.Type: ApplicationFiled: April 5, 2023Publication date: October 12, 2023Applicant: The United States of America, as represented by the Secretary of the NavyInventors: Brandon W. Rudolph, Matthew A. Thompson, Daniel S. Spoor
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Patent number: 9229051Abstract: An integrated circuit including a degradation monitoring circuit. The degradation monitoring circuit includes a comparison circuit having a delay element including an input coupled to a data node of a timing path and having an output to provide a delayed signal of a data signal of the data node. The comparison circuit includes a logic comparator that provides a logic comparison between a data signal of the data node and the output of the delay element. The monitoring circuit includes a sampling circuit that provides a sampled signal of the output of the logic comparator that is a sampled with respect to a clock signal of the clock signal line. The monitoring circuit includes a hold circuit that provides a signal indicative of a data signal of the data node transitioning within a predetermined time of an edge transition of a clock signal of the clock signal line.Type: GrantFiled: November 15, 2012Date of Patent: January 5, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Puneet Sharma, Matthew A. Thompson, Willard E. Conley
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Publication number: 20140132315Abstract: An integrated circuit including a degradation monitoring circuit. The degradation monitoring circuit includes a comparison circuit having a delay element including an input coupled to a data node of a timing path and having an output to provide a delayed signal of a data signal of the data node. The comparison circuit includes a logic comparator that provides a logic comparison between a data signal of the data node and the output of the delay element. The monitoring circuit includes a sampling circuit that provides a sampled signal of the output of the logic comparator that is a sampled with respect to a clock signal of the clock signal line. The monitoring circuit includes a hold circuit that provides a signal indicative of a data signal of the data node transitioning within a predetermined time of an edge transition of a clock signal of the clock signal line.Type: ApplicationFiled: November 15, 2012Publication date: May 15, 2014Inventors: Puneet Sharma, Matthew A. Thompson, Willard E. Conley
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Patent number: 8661393Abstract: A disclosed method for evaluating placement context sensitivity in the design of an integrated circuit includes accessing a standard cell library comprising a database of standard cells and determining generating boundary data for each of the standard cells. The boundary data for a standard cell indicates the layout of features located within boundary regions of the standard cell. The method includes merging or consolidating boundary data for any two standard cells if their boundary data is the same to determine a canonical or minimal set of boundary regions. The disclosed method further includes enumerating and evaluating all combinations of pairs of the canonical boundary regions and, responsive to identifying of a proximity-based sensitivity or exception, modifying, notating, or otherwise remediating the applicable one or more standard cells that correspond to the boundary region combination that raised the exception.Type: GrantFiled: June 28, 2012Date of Patent: February 25, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Robert E. Boone, Puneet Sharma, Matthew A. Thompson
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Publication number: 20140007029Abstract: A disclosed method for evaluating placement context sensitivity in the design of an integrated circuit includes accessing a standard cell library comprising a database of standard cells and determining generating boundary data for each of the standard cells. The boundary data for a standard cell indicates the layout of features located within boundary regions of the standard cell. The method includes merging or consolidating boundary data for any two standard cells if their boundary data is the same to determine a canonical or minimal set of boundary regions. The disclosed method further includes enumerating and evaluating all combinations of pairs of the canonical boundary regions and, responsive to identifying of a proximity-based sensitivity or exception, modifying, notating, or otherwise remediating the applicable one or more standard cells that correspond to the boundary region combination that raised the exception.Type: ApplicationFiled: June 28, 2012Publication date: January 2, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Robert E. Boone, Puneet Sharma, Matthew A. Thompson
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Patent number: 7566220Abstract: The present invention relates to a modular propane gas log burner for use in fireplaces that were originally designed as wood burning fireplaces. The present burner is designed for clean burning of propane fuel and is modular so that more than one burner can be used in combination in order to create a burner configuration for wider single-sided gas log sets, for deeper single-sided gas log sets, and for two-sided or see-through gas log sets. The burner is provided with means for adjusting the fuel-to-air ratio and for adjusting the position of the flames to allow the user to achieve realistic and clean burning flames.Type: GrantFiled: August 29, 2005Date of Patent: July 28, 2009Assignee: Hargrove Manufacturing CorporationInventor: Matthew A. Thompson
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Patent number: 7553437Abstract: A mold assembly for making a molded foam article generally includes a housing having an internal cavity and an opening into the cavity, a movable support member movable between an inner position and an outer position, an object supported by the support member and having a three-dimensional shape, and a closure. A method for making a molded foam article generally includes moving the support member to the outer position, positioning a film web over the object to form a substantially convex envelopment, moving the support member to the inner position while maintaining the film web in contact with the object to reconfigure the substantially convex film envelopment into a partially concave film envelopment, and dispensing a predetermined amount of a foamable composition into the hollow space provided by the concave envelopment.Type: GrantFiled: May 10, 2007Date of Patent: June 30, 2009Assignee: Sealed Air Corporation (US)Inventors: Matthew A. Thompson, Timothy T. Oberle, John J. Corrigan, III, Robert D. Wheeler
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Publication number: 20090108305Abstract: A semiconductor device includes an active semiconductor material. A transistor gate overlies a first portion of the active semiconductor material. A second portion intersects the first portion at a corner which is distorted during manufacture resulting in rounding of the corner. The active semiconductor material extends into the corner to create a concave corner. To reduce the corner rounding, a compensation feature extends from a first edge of the first portion by an amount less than needed to provide an electrical contact structure on the compensation feature. The feature is positioned laterally further away from the corner than the overlying transistor gate. The compensation feature is positioned from the corner by a dimension that is within 0.4 to 0.6 of the wavelength of light used to image features of the semiconductor device. Due to optical distortion the compensation feature itself has a nonlinear shape.Type: ApplicationFiled: October 30, 2007Publication date: April 30, 2009Inventors: Lionel J. Riviere-Cazaux, Matthew A. Thompson
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Publication number: 20080277816Abstract: A mold assembly for making a molded foam article generally includes a housing having an internal cavity and an opening into the cavity, a movable support member movable between an inner position and an outer position, an object supported by the support member and having a three-dimensional shape, and a closure. A method for making a molded foam article generally includes moving the support member to the outer position, positioning a film web over the object to form a substantially convex envelopment, moving the support member to the inner position while maintaining the film web in contact with the object to reconfigure the substantially convex film envelopment into a partially concave film envelopment, and dispensing a predetermined amount of a foamable composition into the hollow space provided by the concave envelopment.Type: ApplicationFiled: May 10, 2007Publication date: November 13, 2008Inventors: Matthew A. Thompson, Timothy T. Oberle, John J. Corrigan, III, Robert D. Wheeler
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Publication number: 20040107361Abstract: A network intrusion detection system for detection of an intrusion through the analysis of data units on a network connection is described herein. The network intrusion detection system provides enhanced memory performance through an interrupt handling routine that minimises calls to the operating system, and mitigates the performance overhead of copying data units from one memory location to another. Data units received from an external network are placed into a ring buffer for in place analysis to reduce data transfer overhead.Type: ApplicationFiled: November 29, 2002Publication date: June 3, 2004Inventors: Michael C. Redan, Matthew A. Thompson
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Patent number: 6352803Abstract: A process for creating a mask substrate involving depositing: 1) a coating on one or both sides of a low thermal expansion material EUVL mask substrate to improve defect inspection, surface finishing, and defect levels; and 2) a high dielectric coating, on the backside to facilitate electrostatic chucking and to correct for any bowing caused by the stress imbalance imparted by either other deposited coatings or the multilayer coating of the mask substrate. An film, such as TaSi, may be deposited on the front side and/or back of the low thermal expansion material before the material coating to balance the stress. The low thermal expansion material with a silicon overlayer and a silicon and/or other conductive underlayer enables improved defect inspection and stress balancing.Type: GrantFiled: June 6, 2000Date of Patent: March 5, 2002Assignee: The Regents of the University of CaliforniaInventors: William Man-Wai Tong, John S. Taylor, Scott D. Hector, Pawitter J. S. Mangat, Alan R. Stivers, Patrick G. Kofron, Matthew A. Thompson
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Patent number: 5885856Abstract: A pattern of dummy structures (20) is added to the layout pattern of an integrated circuit (10) to equilibrate the polishing rate across the surface of a semiconductor substrate (11). The location of each dummy structure (20) is predetermined so that it does not intersect a well boundary (17) or an active region (21,27), and does not fall under a conductive material such as a layer of polysilicon (22,28) or an interconnect structure (23,29).Type: GrantFiled: August 21, 1996Date of Patent: March 23, 1999Assignee: Motorola, Inc.Inventors: Percy V. Gilbert, Subramoney Iyer, Bradley P. Smith, Matthew A. Thompson, Kevin Kemp, Rajive Dhar
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Patent number: 5552247Abstract: A method of patterning an X-ray master mask (21) is described by using reduction projection. An X-ray mask (21) is provided with a photoactive material coating a plating base layer (24). The X-ray mask (21) is positioned under the reduction projection tool. The photoactive material on the X-ray mask (21) is exposed from a pattern (13) in the reduction projection tool.Type: GrantFiled: April 1, 1991Date of Patent: September 3, 1996Assignee: MotorolaInventors: Whitson G. Waldo, III, Matthew A. Thompson
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Patent number: 5268951Abstract: A x-ray scanning method involves the stops of directing an x-ray beam at a collimating first mirror having the capability of altering the source to mirror location and/or grazing angle of incidence. The beam is then reflected from a flat second mirror capable of a scanning motion by linear translation with an optional accompanying angular change in the grazing angle of incidence of the beam on the second mirror.Type: GrantFiled: December 22, 1992Date of Patent: December 7, 1993Assignee: International Business Machines CorporationInventors: Alexander L. Flamholz, Robert P. Rippstein, Jerome P. Silverman, Matthew A. Thompson