Patents by Inventor Matthew Adiletta
Matthew Adiletta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240006375Abstract: Embodiments of a microelectronic assembly comprise: a first plurality of integrated circuit (IC) dies coupled on one end to a first IC die and on an opposing end to a second IC die, and a second plurality of IC dies coupled to at least the first IC die or the second IC die. Each IC die in the first plurality of IC dies includes a respective substrate and a respective metallization stack attached along a respective first planar interface, each of the first IC die and the second IC die includes a respective substrate and a respective metallization stack attached along a respective second planar interface, each IC die in the second plurality of IC dies includes a respective substrate and a respective metallization stack attached along a respective third planar interface, and the first planar interface is orthogonal to the second planar interface.Type: ApplicationFiled: June 29, 2022Publication date: January 4, 2024Inventors: Sagar Suthram, Wilfred Gomes, Pushkar Sharad Ranade, Ravindranath Vithal Mahajan, Debendra Mallik, Omkar G. Karhade, Nitin A. Deshpande, Abhishek A. Sharma, Joshua Fryman, Stephen Morein, Matthew Adiletta
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Publication number: 20230420411Abstract: Embodiments of an integrated circuit (IC) die comprise: a metallization stack including a dielectric material, a plurality of layers of conductive traces in the dielectric material and conductive vias through the dielectric material; and a substrate attached to the metallization stack along a planar interface. The metallization stack comprises bond-pads on a first surface, a second surface, a third surface, a fourth surface, and a fifth surface. The first surface is parallel to the planar interface between the metallization stack and the substrate, the second surface is parallel to the third surface and orthogonal to the first surface, and the fourth surface is parallel to the fifth surface and orthogonal to the first surface and the second surface.Type: ApplicationFiled: June 22, 2022Publication date: December 28, 2023Applicant: Intel CorporationInventors: Sagar Suthram, Ravindranath Vithal Mahajan, Debendra Mallik, Omkar G. Karhade, Wilfred Gomes, Pushkar Sharad Ranade, Abhishek A. Sharma, Tahir Ghani, Anand S. Murthy, Nitin A. Deshpande, Joshua Fryman, Stephen Morein, Matthew Adiletta
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Publication number: 20230420409Abstract: Embodiments of an integrated circuit (IC) die comprise: a first region having a first surface and a second surface, the first surface being orthogonal to the second surface; and a second region attached to the first region along a planar interface that is orthogonal to the first surface and parallel to the second surface, the second region having a third surface coplanar with the first surface. The first region comprises: a dielectric material; layers of conductive traces in the dielectric material, each layer of the conductive traces being parallel to the second surface such that the conductive traces are orthogonal to the first surface; conductive vias through the dielectric material; and bond-pads on the first surface, the bond-pads comprising portions of the conductive traces exposed on the first surface, and the second region comprises a material different from the dielectric material.Type: ApplicationFiled: June 22, 2022Publication date: December 28, 2023Applicant: Intel CorporationInventors: Sagar Suthram, Omkar G. Karhade, Ravindranath Vithal Mahajan, Debendra Mallik, Nitin A. Deshpande, Pushkar Sharad Ranade, Wilfred Gomes, Abhishek A. Sharma, Tahir Ghani, Anand S. Murthy, Joshua Fryman, Stephen Morein, Matthew Adiletta, Michael Crocker, Aaron Gorius
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Patent number: 11789641Abstract: A three dimensional circuit system includes a first integrated circuit die having a core logic region that has first memory circuits and logic circuits. The three dimensional circuit system includes a second integrated circuit die that has second memory circuits. The first and second integrated circuit dies are coupled together in a vertically stacked configuration. The three dimensional circuit system includes third memory circuits coupled to the first integrated circuit die. The third memory circuits reside in a plane of the first integrated circuit die. The logic circuits are coupled to access the first, second, and third memory circuits and data can move between the first, second, and third memories. The third memory circuits have a larger memory capacity and a smaller memory access bandwidth than the second memory circuits. The second memory circuits have a larger memory capacity and a smaller memory access bandwidth than the first memory circuits.Type: GrantFiled: June 16, 2021Date of Patent: October 17, 2023Assignee: Intel CorporationInventors: Scott Weber, Jawad Khan, Ilya Ganusov, Martin Langhammer, Matthew Adiletta, Terence Magee, Albert Fazio, Richard Coulson, Ravi Gutala, Aravind Dasu, Mahesh Iyer
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Publication number: 20230185658Abstract: An example of an electronic apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to control access to a memory for a range of addresses within a memory address space, configure a first region of the memory within a first sub-range of addresses within the memory address space to be accessed with a first protection level of two or more memory fault protection levels, and configure a second region of the memory within a second sub-range of addresses within the memory address space that is non-overlapping with the first sub-range to be accessed with a second protection level of the two or more memory fault protection levels. Other examples are disclosed and claimed.Type: ApplicationFiled: February 10, 2023Publication date: June 15, 2023Applicant: Intel CorporationInventors: Duane Galbi, Matthew Adiletta
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Publication number: 20230098017Abstract: Technologies for switching network traffic include a network switch. The network switch includes one or more processors and communication circuitry coupled to the one or more processors. The communication circuity is capable of switching network traffic of multiple link layer protocols. Additionally, the network switch includes one or more memory devices storing instructions that, when executed, cause the network switch to receive, with the communication circuitry through an optical connection, network traffic to be forwarded, and determine a link layer protocol of the received network traffic. The instructions additionally cause the network switch to forward the network traffic as a function of the determined link layer protocol. Other embodiments are also described and claimed.Type: ApplicationFiled: December 6, 2022Publication date: March 30, 2023Applicant: Intel CorporationInventors: Matthew Adiletta, Aaron Gorius, Myles Wilde, Michael Crocker
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Patent number: 11595277Abstract: Technologies for switching network traffic include a network switch. The network switch includes one or more processors and communication circuitry coupled to the one or more processors. The communication circuitry is capable of switching network traffic of multiple link layer protocols. Additionally, the network switch includes one or more memory devices storing instructions that, when executed, cause the network switch to receive, with the communication circuitry through an optical connection, network traffic to be forwarded, and determine a link layer protocol of the received network traffic. The instructions additionally cause the network switch to forward the network traffic as a function of the determined link layer protocol. Other embodiments are also described and claimed.Type: GrantFiled: August 17, 2021Date of Patent: February 28, 2023Assignee: Intel CorporationInventors: Matthew Adiletta, Aaron Gorius, Myles Wilde, Michael Crocker
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Publication number: 20220405005Abstract: A three dimensional circuit system includes a first integrated circuit die having a core logic region that has first memory circuits and logic circuits. The three dimensional circuit system includes a second integrated circuit die that has second memory circuits. The first and second integrated circuit dies are coupled together in a vertically stacked configuration. The three dimensional circuit system includes third memory circuits coupled to the first integrated circuit die. The third memory circuits reside in a plane of the first integrated circuit die. The logic circuits are coupled to access the first, second, and third memory circuits and data can move between the first, second, and third memories. The third memory circuits have a larger memory capacity and a smaller memory access bandwidth than the second memory circuits. The second memory circuits have a larger memory capacity and a smaller memory access bandwidth than the first memory circuits.Type: ApplicationFiled: June 16, 2021Publication date: December 22, 2022Applicant: Intel CorporationInventors: Scott Weber, Jawad Khan, Ilya Ganusov, Martin Langhammer, Matthew Adiletta, Terence Magee, Albert Fazio, Richard Coulson, Ravi Gutala, Aravind Dasu, Mahesh Iyer
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Publication number: 20210377140Abstract: Technologies for switching network traffic include a network switch. The network switch includes one or more processors and communication circuitry coupled to the one or more processors. The communication circuity is capable of switching network traffic of multiple link layer protocols. Additionally, the network switch includes one or more memory devices storing instructions that, when executed, cause the network switch to receive, with the communication circuitry through an optical connection, network traffic to be forwarded, and determine a link layer protocol of the received network traffic. The instructions additionally cause the network switch to forward the network traffic as a function of the determined link layer protocol. Other embodiments are also described and claimed.Type: ApplicationFiled: August 17, 2021Publication date: December 2, 2021Applicant: Intel CorporationInventors: Matthew Adiletta, Aaron Gorius, Myles Wilde, Michael Crocker
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Patent number: 11128553Abstract: Technologies for switching network traffic include a network switch. The network switch includes one or more processors and communication circuitry coupled to the one or more processors. The communication circuitry is capable of switching network traffic of multiple link layer protocols. Additionally, the network switch includes one or more memory devices storing instructions that, when executed, cause the network switch to receive, with the communication circuitry through an optical connection, network traffic to be forwarded, and determine a link layer protocol of the received network traffic. The instructions additionally cause the network switch to forward the network traffic as a function of the determined link layer protocol. Other embodiments are also described and claimed.Type: GrantFiled: September 9, 2020Date of Patent: September 21, 2021Assignee: Intel CorporationInventors: Matthew Adiletta, Aaron Gorius, Myles Wilde, Michael Crocker
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Publication number: 20210058308Abstract: Technologies for switching network traffic include a network switch. The network switch includes one or more processors and communication circuitry coupled to the one or more processors. The communication circuitry is capable of switching network traffic of multiple link layer protocols. Additionally, the network switch includes one or more memory devices storing instructions that, when executed, cause the network switch to receive, with the communication circuitry through an optical connection, network traffic to be forwarded, and determine a link layer protocol of the received network traffic. The instructions additionally cause the network switch to forward the network traffic as a function of the determined link layer protocol. Other embodiments are also described and claimed.Type: ApplicationFiled: September 9, 2020Publication date: February 25, 2021Applicant: Intel CorporationInventors: Matthew Adiletta, Aaron Gorius, Myles Wilde, Michael Crocker
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Patent number: 10802229Abstract: Technologies for switching network traffic include a network switch. The network switch includes one or more processors and communication circuitry coupled to the one or more processors. The communication circuitry is capable of switching network traffic of multiple link layer protocols. Additionally, the network switch includes one or more memory devices storing instructions that, when executed, cause the network switch to receive, with the communication circuitry through an optical connection, network traffic to be forwarded, and determine a link layer protocol of the received network traffic. The instructions additionally cause the network switch to forward the network traffic as a function of the determined link layer protocol. Other embodiments are also described and claimed.Type: GrantFiled: August 6, 2018Date of Patent: October 13, 2020Assignee: Intel CorporationInventors: Matthew Adiletta, Aaron Gorius, Myles Wilde, Michael Crocker
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Patent number: 10791384Abstract: Technologies for switching network traffic include a network switch. The network switch includes one or more processors and communication circuitry coupled to the one or more processors. The communication circuitry is capable of switching network traffic of multiple link layer protocols. Additionally, the network switch includes one or more memory devices storing instructions that, when executed, cause the network switch to receive, with the communication circuitry through an optical connection, network traffic to be forwarded, and determine a link layer protocol of the received network traffic. The instructions additionally cause the network switch to forward the network traffic as a function of the determined link layer protocol. Other embodiments are also described and claimed.Type: GrantFiled: July 16, 2019Date of Patent: September 29, 2020Assignee: Intel CorporationInventors: Matthew Adiletta, Aaron Gorius, Myles Wilde, Michael Crocker
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Patent number: 10785549Abstract: Technologies for switching network traffic include a network switch. The network switch includes one or more processors and communication circuitry coupled to the one or more processors. The communication circuitry is capable of switching network traffic of multiple link layer protocols. Additionally, the network switch includes one or more memory devices storing instructions that, when executed, cause the network switch to receive, with the communication circuitry through an optical connection, network traffic to be forwarded, and determine a link layer protocol of the received network traffic. The instructions additionally cause the network switch to forward the network traffic as a function of the determined link layer protocol. Other embodiments are also described and claimed.Type: GrantFiled: July 16, 2019Date of Patent: September 22, 2020Assignee: Intel CorporationInventors: Matthew Adiletta, Aaron Gorius, Myles Wilde, Michael Crocker
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Publication number: 20190342643Abstract: Technologies for switching network traffic include a network switch. The network switch includes one or more processors and communication circuitry coupled to the one or more processors. The communication circuity is capable of switching network traffic of multiple link layer protocols. Additionally, the network switch includes one or more memory devices storing instructions that, when executed, cause the network switch to receive, with the communication circuitry through an optical connection, network traffic to be forwarded, and determine a link layer protocol of the received network traffic. The instructions additionally cause the network switch to forward the network traffic as a function of the determined link layer protocol. Other embodiments are also described and claimed.Type: ApplicationFiled: July 16, 2019Publication date: November 7, 2019Inventors: Matthew Adiletta, Aaron Gorius, Myles Wilde, Michael Crocker
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Publication number: 20190342642Abstract: Technologies for switching network traffic include a network switch. The network switch includes one or more processors and communication circuitry coupled to the one or more processors. The communication circuitry is capable of switching network traffic of multiple link layer protocols. Additionally, the network switch includes one or more memory devices storing instructions that, when executed, cause the network switch to receive, with the communication circuitry through an optical connection, network traffic to be forwarded, and determine a link layer protocol of the received network traffic. The instructions additionally cause the network switch to forward the network traffic as a function of the determined link layer protocol. Other embodiments are also described and claimed.Type: ApplicationFiled: July 16, 2019Publication date: November 7, 2019Inventors: Matthew Adiletta, Aaron Gorius, Myles Wilde, Michael Crocker
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Publication number: 20190014396Abstract: Technologies for switching network traffic include a network switch. The network switch includes one or more processors and communication circuitry coupled to the one or more processors. The communication circuitry is capable of switching network traffic of multiple link layer protocols. Additionally, the network switch includes one or more memory devices storing instructions that, when executed, cause the network switch to receive, with the communication circuitry through an optical connection, network traffic to be forwarded, and determine a link layer protocol of the received network traffic. The instructions additionally cause the network switch to forward the network traffic as a function of the determined link layer protocol. Other embodiments are also described and claimed.Type: ApplicationFiled: August 6, 2018Publication date: January 10, 2019Inventors: Matthew Adiletta, Aaron Gorius, Myles Wilde, Michael Crocker
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Patent number: 10045098Abstract: Technologies for switching network traffic include a network switch. The network switch includes one or more processors and communication circuitry coupled to the one or more processors. The communication circuity is capable of switching network traffic of multiple link layer protocols. Additionally, the network switch includes one or more memory devices storing instructions that, when executed, cause the network switch to receive, with the communication circuitry through an optical connection, network traffic to be forwarded, and determine a link layer protocol of the received network traffic. The instructions additionally cause the network switch to forward the network traffic as a function of the determined link layer protocol. Other embodiments are also described and claimed.Type: GrantFiled: December 30, 2016Date of Patent: August 7, 2018Assignee: Intel CorporationInventors: Matthew Adiletta, Aaron Gorius, Myles Wilde, Michael Crocker
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Publication number: 20180027312Abstract: Technologies for switching network traffic include a network switch. The network switch includes one or more processors and communication circuitry coupled to the one or more processors. The communication circuity is capable of switching network traffic of multiple link layer protocols. Additionally, the network switch includes one or more memory devices storing instructions that, when executed, cause the network switch to receive, with the communication circuitry through an optical connection, network traffic to be forwarded, and determine a link layer protocol of the received network traffic. The instructions additionally cause the network switch to forward the network traffic as a function of the determined link layer protocol. Other embodiments are also described and claimed.Type: ApplicationFiled: December 30, 2016Publication date: January 25, 2018Inventors: Matthew Adiletta, Aaron Gorius, Myles Wilde, Michael Crocker
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Patent number: 9544347Abstract: Methods and apparatus relating to distribution of intelligence across a network are described. In one embodiment, one or more content processors may be provided at the edge of a computer network (e.g., prior to a point where data is aggregated or routed by the network). Other embodiments are also disclosed.Type: GrantFiled: December 26, 2014Date of Patent: January 10, 2017Assignee: Intel CorporationInventors: Jeffrey G. Fedders, Matthew Adiletta, Valerie J. Young