Abstract: Devices and methods include transmitting loopback signals for monitoring operation of a memory device. In some embodiments, a memory device may receive a system clock signal from a host device and may generate an internal clock signal based at least in part on the system clock signal. In some embodiments, the memory device may generate a loopback signal based at least in part on the internal clock signal and may transmit the loopback signal via a loopback datapath associated with the memory device. A host device may compare the internal clock signal and the system clock signal to determine a fidelity of the internal clock signal. Termination values of the memory device may be adjusted based on the determined fidelity of the internal clock signal.

Abstract: The systems and methods described herein relate to a bi-directional data path (DQ) symbol map generated based on error correction operations. A device may include sub-wordline drivers and bi-directional data paths (DQs) that couple between the sub-wordline drivers and input/output (I/O) interface circuitry based on assignments indicated by the DQ symbol map. The assignments may be generated based on error correction operations performed on data of the memory bank. In particular, the DQ symbol map may be generated to avoid some conditions that, if occurring, may render one or more data errors uncorrectable. These systems and methods may reduce a likelihood of a data error associated with a DQ being uncorrectable.

Abstract: The systems and methods described herein relate to a bi-directional data path (DQ) symbol map generated based on error correction operations. A device may include sub-wordline drivers and bi-directional data paths (DQs) that couple between the sub-wordline drivers and input/output (I/O) interface circuitry based on assignments indicated by the DQ symbol map. The assignments may be generated based on error correction operations performed on data of the memory bank. In particular, the DQ symbol map may be generated to avoid some conditions that, if occurring, may render one or more data errors uncorrectable. These systems and methods may reduce a likelihood of a data error associated with a DQ being uncorrectable.

Abstract: One embodiment of the present disclosure describes a loopback network including a loopback datapath and a plurality of memory devices. The plurality of memory devices may include a first memory device coupled to a first trunk connector of the first loopback datapath via a first branch connector. The plurality of memory devices may also include a second memory device coupled to the first trunk connector of the first loopback datapath via a second branch connector. When data communicated with the first memory device is targeted by loopback parameters, the first memory device may output a first loopback data signal generated based at least in part on the first data to the first loopback datapath, and the second memory device may block output from the second memory device to the first loopback datapath.

Abstract: One embodiment of the present disclosure describes a loopback network including a loopback datapath and a plurality of memory devices. The plurality of memory devices may include a first memory device coupled to a first trunk connector of the first loopback datapath via a first branch connector. The plurality of memory devices may also include a second memory device coupled to the first trunk connector of the first loopback datapath via a second branch connector. When data communicated with the first memory device is targeted by loopback parameters, the first memory device may output a first loopback data signal generated based at least in part on the first data to the first loopback datapath, and the second memory device may block output from the second memory device to the first loopback datapath.