Patents by Inventor Matthew Angyal
Matthew Angyal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11011415Abstract: Multiple interconnect structures with reduced TDDB susceptibility and reduced stray capacitance are disclosed. The structures have one or more pairs of layers (an upper and a lower layer) that form layered pairs in the structure. In each of the upper and lower layers, dielectric material separates an upper pair of interconnects from a lower pair of interconnects or from other conductive material. Pairs of vias pass through the dielectric and mechanically and electrically connect the respective sides of the upper and lower sides of the interconnect. A gap of air separates all or part of the pair of vias and the electrical paths the vias are within. In alternative embodiments, the airgap may extend to the bottom of the vias, below the tops of the lower pair of interconnects, or deeper into the lower layer. Alternative process methods are disclosed for making the different embodiments of the structures.Type: GrantFiled: April 24, 2020Date of Patent: May 18, 2021Assignee: International Business Machines CorporationInventors: Rasit O. Topaloglu, Naftali Lustig, Matthew Angyal
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Patent number: 10796949Abstract: Multiple interconnect structures with reduced TDDB susceptibility and reduced stray capacitance are disclosed. The structures have one or more pairs of layers (an upper and a lower layer) that form layered pairs in the structure. In each of the upper and lower layers, dielectric material separates an upper pair of interconnects from a lower pair of interconnects or from other conductive material. Pairs of vias pass through the dielectric and mechanically and electrically connect the respective sides of the upper and lower sides of the interconnect. A gap of air separates all or part of the pair of vias and the electrical paths the vias are within. In alternative embodiments, the airgap may extend to the bottom of the vias, below the tops of the lower pair of interconnects, or deeper into the lower layer. Alternative process methods are disclosed for making the different embodiments of the structures.Type: GrantFiled: October 19, 2018Date of Patent: October 6, 2020Assignee: International Business Machines CorporationInventors: Rasit O. Topaloglu, Naftali Lustig, Matthew Angyal
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Publication number: 20200258770Abstract: Multiple interconnect structures with reduced TDDB susceptibility and reduced stray capacitance are disclosed. The structures have one or more pairs of layers (an upper and a lower layer) that form layered pairs in the structure. In each of the upper and lower layers, dielectric material separates an upper pair of interconnects from a lower pair of interconnects or from other conductive material. Pairs of vias pass through the dielectric and mechanically and electrically connect the respective sides of the upper and lower sides of the interconnect. A gap of air separates all or part of the pair of vias and the electrical paths the vias are within. In alternative embodiments, the airgap may extend to the bottom of the vias, below the tops of the lower pair of interconnects, or deeper into the lower layer. Alternative process methods are disclosed for making the different embodiments of the structures.Type: ApplicationFiled: April 24, 2020Publication date: August 13, 2020Inventors: Rasit O. Topaloglu, Naftali Lustig, Matthew Angyal
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Publication number: 20200126842Abstract: Multiple interconnect structures with reduced TDDB susceptibility and reduced stray capacitance are disclosed. The structures have one or more pairs of layers (an upper and a lower layer) that form layered pairs in the structure. In each of the upper and lower layers, dielectric material separates an upper pair of interconnects from a lower pair of interconnects or from other conductive material. Pairs of vias pass through the dielectric and mechanically and electrically connect the respective sides of the upper and lower sides of the interconnect. A gap of air separates all or part of the pair of vias and the electrical paths the vias are within. In alternative embodiments, the airgap may extend to the bottom of the vias, below the tops of the lower pair of interconnects, or deeper into the lower layer. Alternative process methods are disclosed for making the different embodiments of the structures.Type: ApplicationFiled: October 19, 2018Publication date: April 23, 2020Inventors: Rasit O. Topaloglu, Naftali Lustig, Matthew Angyal
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Patent number: 8822342Abstract: A method of forming a device is disclosed. The method includes providing a substrate prepared with a dielectric layer having first and second regions. The first region comprises wide features and the second region comprises narrow features. A depth delta exists between bottoms of the wide and narrow features. A non-conformal layer is formed on the substrate and it lines the wide and narrow trenches in the first and second regions. The non-conformal layer is removed. Removing the non-conformal layer reduces the depth delta between the bottoms of the wide and narrow features in the first and second region.Type: GrantFiled: December 30, 2010Date of Patent: September 2, 2014Assignees: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Ravi Prakash Srivastava, Oluwafemi. O. Ogunsola, Craig Child, Muhammed Shafi Kurikka Valappil Pallachalil, Habib Hichri, Matthew Angyal, Hideshi Miyajima
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Patent number: 8350359Abstract: An aluminum lateral interconnect of a Back End of the Line (BEOL) is used to define the x and y dimensions of a through-silicon via in a semiconductor chip formed in a silicon substrate. The TSV includes one or more aluminum annulus formed on a surface of the substrate, and a deep trench in the substrate having a diameter that is determined by the diameter of the aluminum annulus. The annulus can also be provided with a conductive strap upon which a capacitor can be formed. The strap can also be used to provide a connection of the TSV to other BEOL interconnects.Type: GrantFiled: August 11, 2009Date of Patent: January 8, 2013Assignee: International Business Machines CorporationInventors: Kevin S. Petrarca, Matthew Angyal, Lawrence A. Clevenger, Carl Radens, Brian C. Sapp
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Publication number: 20120168957Abstract: A method of forming a device is disclosed. The method includes providing a substrate prepared with a dielectric layer having first and second regions. The first region comprises wide features and the second region comprises narrow features. A depth delta exists between bottoms of the wide and narrow features. A non-conformal layer is formed on the substrate and it lines the wide and narrow trenches in the first and second regions. The non-conformal layer is removed. Removing the non-conformal layer reduces the depth delta between the bottoms of the wide and narrow features in the first and second region.Type: ApplicationFiled: December 30, 2010Publication date: July 5, 2012Applicants: GLOBALFOUNDRIES SINGAPORE PTE. LTD., INTERNATIONAL BUSINESS MACHINES CORPORATION, TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC., INFINEON TECHNOLOGIES NORTH AMERICA CORP., ADVANCED MICRO DEVICES CORPORATIONInventors: Ravi Prakash SRIVASTAVA, Oluwafemi O. OGUNSOLA, Craig CHILD, Muhammed Shafi Kurikka Valappil PALLACHALIL, Habib HICHRI, Matthew ANGYAL, Hideshi MIYAJIMA
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Publication number: 20110037143Abstract: An aluminum lateral interconnect of a Back End of the Line (BEOL) is used to define the x and y dimensions of a through-silicon via in a semiconductor chip formed in a silicon substrate. The TSV includes one or more aluminum annulus formed on a surface of the substrate, and a deep trench in the substrate having a diameter that is determined by the diameter of the aluminum annulus. The annulus can also be provided with a conductive strap upon which a capacitor can be formed. The strap can also be used to provide a connection of the TV to other BEOL interconnects.Type: ApplicationFiled: August 11, 2009Publication date: February 17, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin S. Petrarca, Matthew Angyal, Lawrence A. Clevenger, Carl Radens, Brian C. Sapp
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Publication number: 20090031260Abstract: A method, computer program and system for the optimization of semiconductor process parameters given a pre-specified set of targets and constraints on electrical performance metrics are disclosed. Semiconductor process engineers who are not expert in the art of electrical analysis or mathematical optimization can readily use the method of this invention in optimizing semiconductor process parameters. Accommodates the differences in design styles, metal layer routing, and electrical metrics using priority schedules that are easy to input and understand. Enables the exploration of the process parameter space using primitive process tolerances and accurate electrical information provided by field solvers and circuit analysis programs.Type: ApplicationFiled: July 25, 2007Publication date: January 29, 2009Inventors: Matthew Angyal, Alina Deutsch, Ibrahim M. Elfadel, Raminderpal Singh, Theodorus E. Standaert, Wayne H. Woods
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Publication number: 20090026587Abstract: A dielectric layer for a semiconductor device having a low overall dielectric constant, good adhesion to the semiconductor substrate, and good resistance to cracking due to thermal cycling. The dielectric layer is made by a process involving continuous variation of dielectric material deposition conditions to provide a dielectric layer having a gradient of dielectric constant.Type: ApplicationFiled: January 14, 2004Publication date: January 29, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew Angyal, Habib Hichri, Henry A. Nye, III, Dale McHerron, Jia Lee
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Patent number: 7325225Abstract: It is important to assess and reduce errors that arise in mask correction techniques such as optical proximity correction. A preliminary mask is obtained using an OPC model. An etched wafer is created from the preliminary mask using lithography, and first and second critical dimensions (CD) are measured on the wafer and. An edge placement error (EPE) is determined that corresponds to a difference between a measured value and a desired value of the second CD. These steps are repeated for a plurality of different values of the first CD, and of for each of the values of, the measured value of the second CD is correlated with its corresponding value on the mask as predicted by the OPC model. ? difference ?CD is obtained between the difference of the mask CDs calculated by interpolation of wafer CD measurements and by OPC model predictions and is transformed into an OPC model error.Type: GrantFiled: October 5, 2005Date of Patent: January 29, 2008Inventors: Yasushi Tanaka, Masahiro Inohara, Matthew Angyal
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Publication number: 20070174796Abstract: A system, a method and a computer program product for analyzing a circuit design provide for discretizing the circuit design into a series of pixels. A fraction of at least one constituent material is determined for each pixel. A deflection is also determined for each pixel. The deflection is predicated upon a planarizing of the pixel, and it is calculated while utilizing an algorithm that includes the fraction of the at least one constituent material. A series of deflections for the series of pixels may be mapped and evaluated.Type: ApplicationFiled: January 20, 2006Publication date: July 26, 2007Applicant: International Business Machines CorporationInventors: Matthew Angyal, Giovanni Fiorenza, Habib Hichri, Andrew Lu, Dale McHerron, Conal Murray
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Publication number: 20070079278Abstract: A method is provided of accessing model error in an optical proximity correction (OPC) model. The method begins by obtaining a preliminary mask using an OPC model, creating an etched wafer from the preliminary mask using lithography, and measuring a specified critical dimension (CD) on the wafer and a second CD on the wafer. An edge placement error (EPE) is determined that corresponds to a difference between a measured value of the second CD on the wafer and a desired value of the second CD on the wafer. The aforementioned steps are repeated for a plurality of different values of the specified CD to obtain an EPE for each of the different values of the specified CD. For each of the plurality of values of the specified CD, a measured value of a second CD on the wafer is correlated with a corresponding value of the second CD on the mask.Type: ApplicationFiled: October 5, 2005Publication date: April 5, 2007Inventors: Yasushi Tanaka, Masahiro Inohara, Matthew Angyal
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Publication number: 20060161412Abstract: Techniques are disclosed for determination of parameter variability for one or more given interconnects of a plurality of interconnects in a simulated semiconductor circuit. The simulated semiconductor circuit is defined at least in part by a plurality of input parameters. From a distribution of first values of a given input parameter, a plurality of the first values are determined to use when calculating a corresponding plurality of second values for each of one or more output parameters. By using at least the determined plurality of first values for the given input parameter and selected values for other input parameters in the plurality of input parameters, the corresponding plurality of second values are calculated for each of the one or more output parameters. The one or more output parameters correspond to the one or more given interconnects. Each of the second values corresponds to one of the determined plurality of first values.Type: ApplicationFiled: January 18, 2005Publication date: July 20, 2006Applicant: International Business Machines CorporationInventors: Matthew Angyal, Alina Deutsch, Ibrahim Elfadel, Zhichao Zhang
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Patent number: 7009280Abstract: An interlevel dielectric layer (ILD) comprises a low-k dielectric layer; and a low-k dielectric film, deposited under compressive stress, atop the dielectric layer. The dielectric layer comprises a low-k material, such as an organosilicon glass (OSG) or a SiCOH material. The dielectric film has a thickness, which is 2%–10% of the thickness of the dielectric layer, has a similar chemical composition to the dielectric layer, but has a different morphology than the dielectric layer. The dielectric film is deposited under compressive stress, in situ, at or near the end of the dielectric layer deposition by altering a process that was used to deposit the low-k dielectric layer.Type: GrantFiled: April 28, 2004Date of Patent: March 7, 2006Assignee: International Business Machines CorporationInventors: Matthew Angyal, Edward Paul Barth, Sanjit Kumar Das, Charles Robert Davis, Habib Hichri, William Francis Landers, Jia Lee
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Publication number: 20060024961Abstract: Methods for sealing an organic ILD layer and a metal layer after an etching step. The method includes etching through an ILD layer and leaving a remaining portion of an underlying metal layer cap, maintaining the device in an inert gas, and depositing at least a portion of a liner into the opening to seal the ILD layer and the metal layer. Subsequent processing may include formation of a via by etching through the portion of the liner and the remaining portion of the cap layer, and depositing a metal.Type: ApplicationFiled: July 29, 2004Publication date: February 2, 2006Inventors: Matthew Angyal, Peter Biolsi, Lawrence Clevenger, Habib Hichri, Bernd Kastenmeier, Michael Lane, Jeffrey Marino, Vincent McGahay, Theodorus Standaert
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Publication number: 20050242414Abstract: An interlevel dielectric layer (ILD) comprises a low-k dielectric layer; and a low-k dielectric film, deposited under compressive stress, atop the dielectric layer. The dielectric layer comprises a low-k material, such as an organosilicon glass (OSG) or a SiCOH material. The dielectric film has a thickness, which is 2%-10% of the thickness of the dielectric layer, has a similar chemical composition to the dielectric layer, but has a different morphology than the dielectric layer. The dielectric film is deposited under compressive stress, in situ, at or near the end of the dielectric layer deposition by altering a process that was used to deposit the low-k dielectric layer.Type: ApplicationFiled: April 28, 2004Publication date: November 3, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew Angyal, Edward Barth, Sanjit Das, Charles Davis, Habib Hichri, William Landers, Jia Lee
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Publication number: 20050086615Abstract: A computer aided design (CAD) system. A template generation engine generates templates from interconnect configuration files. A field solver generates high frequency passive element relationships from the templates. A circuit builder generates circuit description files from device technology models and from high frequency passive element relationships. Parameterized circuit description models may be generated for large range of sensitivity analyses. A simulator simulates circuit responses for transmission line models from the circuit description files. Interconnect configuration files may be generated by a geometry and material definition module that receives process description data from a designer.Type: ApplicationFiled: October 21, 2003Publication date: April 21, 2005Inventors: Minakshisundaran Anand, Matthew Angyal, Alina Deutsch, Ibrahim Elfadel, Gerard Kopcsay, Barry Rubin, Howard Smith
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Publication number: 20050023693Abstract: An advanced back-end-of-line (BEOL) interconnect structure having a hybrid dielectric is disclosed. The inter-layer dielectric (ILD) for the via level is preferably different from the ILD for the line level. In a preferred embodiment, the via-level ILD is formed of a low-k SiCOH material, and the line-level ILD is formed of a low-k polymeric thermoset material.Type: ApplicationFiled: July 29, 2004Publication date: February 3, 2005Inventors: John Fitzsimmons, Stephen Greco, Jia Lee, Stephen Gates, Terry Spooner, Matthew Angyal, Habib Hichri, Theordorus Standaert, Glenn Biery