Patents by Inventor Matthew Areno

Matthew Areno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230275758
    Abstract: A processing device includes a non-volatile memory (NVM), provisioning circuitry to receive a provision key and provision data encrypted with the provision key, and to store the encrypted provision data in the NVM, exclusive-OR (XOR) circuitry to perform an XOR operation on the provision key and a physically unclonable function (PUF) mask to generate a masked provision key, and encryption circuitry to encrypt the masked provision key with a PUF key to generate an encrypted provision key. The provisioning circuitry is to store the encrypted provision key in the NVM.
    Type: Application
    Filed: May 5, 2023
    Publication date: August 31, 2023
    Applicant: Intel Corporation
    Inventor: Matthew Areno
  • Publication number: 20210119812
    Abstract: A method comprises receiving a first PUF bitstring from a physically unclonable function (PUF) device, generating, during a provisioning process, a series of match bits, wherein each bit in the series of match bits indicates whether a first PUF bit in the first PUF bitstring matches a corresponding encryption key bit in an encryption key, and using at least a portion of the series of match bits to recreate, during an authentication process, the encryption key.
    Type: Application
    Filed: December 23, 2020
    Publication date: April 22, 2021
    Applicant: Intel Corporation
    Inventor: MATTHEW ARENO
  • Patent number: 9208355
    Abstract: Techniques and mechanisms for providing a value from physically unclonable function (PUF) circuitry for a cryptographic operation of a security module. In an embodiment, a cryptographic engine receives a value from PUF circuitry and based on the value, outputs a result of a cryptographic operation to a bus of the security module. The bus couples the cryptographic engine to control logic or interface logic of the security module. In another embodiment, the value is provided to the cryptographic engine from the PUF circuitry via a signal line which is distinct from the bus, where any exchange of the value by either of the cryptographic engine and the PUF circuitry is for communication of the first value independent of the bus.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: December 8, 2015
    Assignee: Sandia Corporation
    Inventor: Matthew Areno