Abstract: A cache memory circuit capable of dealing with multiple conflicting requests to a given cache line is disclosed. In response to receiving an acquire request for the given cache line from a particular lower-level cache memory circuit, the cache memory circuit sends probe requests regarding the given cache line to other lower-level cache memory circuits. In situations where a different lower-level cache memory circuit is simultaneously trying to evict the given cache line at the particular lower-level cache memory circuit is trying to obtain a copy of the cache line, the cache memory circuit performs a series of operations to service both requests and ensure that the particular lower-level cache memory circuit receives a copy of the given cache line that includes any changes in the evicted copy of the given cache line.

Abstract: A queue circuit that manages access to a memory circuit in a computer system includes multiple sets of entries for storing access requests. The entries in one set of entries are assigned to corresponding sources that generate access requests to the memory circuit. The entries in the other set of entries are floating entries that can be used to store requests from any of the sources. Upon receiving a request from a particular source, the queue circuit checks the entry assigned to the particular source and, if the entry is unoccupied, the queue circuit stores the request in the entry. If, however, the entry assigned to the particular source is occupied, the queue circuit stores the request in one of the floating entries.

Abstract: A cache memory circuit capable of dealing with multiple conflicting requests to a given cache line is disclosed. In response to receiving an acquire request for the given cache line from a particular lower-level cache memory circuit, the cache memory circuit sends probe requests regarding the given cache line to other lower-level cache memory circuits. In situations where a different lower-level cache memory circuit is simultaneously trying to evict the given cache line at the particular lower-level cache memory circuit is trying to obtain a copy of the cache line, the cache memory circuit performs a series of operations to service both requests and ensure that the particular lower-level cache memory circuit receives a copy of the given cache line that includes any changes in the evicted copy of the given cache line.

Abstract: An instruction storage circuit within a processor that includes an instruction memory and a memory control circuit. The instruction memory is configured to store instructions of a program for the processor. The memory control circuit is configured to receive a particular instruction from the instruction memory, detect a data integrity error in the particular instruction, and generate and store a corrected version of the particular instruction in an error storage circuit within the instruction memory. A flush of an execution pipeline may be performed in response to the error. In response to a refetch of the particular instruction after the pipeline flush, the instruction storage circuit may be configured to cause the particular instruction to be provided from the error storage circuit to the execution pipeline to permit forward progress of the processor.

Abstract: The present disclosure is directed to a mechanism for forcing a processor to enter a debug mode. In one embodiment, a processor includes a logic circuit configured to receive a halt request. In response to receiving the halt request while the processor is not in a quiescent state, the logic circuit forces the processor into the quiescent state after a threshold amount of time has elapsed. Processor operation is then halted, and the processor thus becomes accessible for a debugger to perform debug operations.

Abstract: An instruction storage circuit within a processor that includes an instruction memory and a memory control circuit. The instruction memory is configured to store instructions of a program for the processor. The memory control circuit is configured to receive a particular instruction from the instruction memory, detect a data integrity error in the particular instruction, and generate and store a corrected version of the particular instruction in an error storage circuit within the instruction memory. A flush of an execution pipeline may be performed in response to the error. In response to a refetch of the particular instruction after the pipeline flush, the instruction storage circuit may be configured to cause the particular instruction to be provided from the error storage circuit to the execution pipeline to permit forward progress of the processor.

Abstract: The present disclosure is directed to a mechanism for forcing a processor to enter a debug mode. In one embodiment, a processor includes a logic circuit configured to receive a halt request. In response to receiving the halt request while the processor is not in a quiescent state, the logic circuit forces the processor into the quiescent state after a threshold amount of time has elapsed. Processor operation is then halted, and the processor thus becomes accessible for a debugger to perform debug operations.

Abstract: Techniques are disclosed relating to using non-debug path circuitry to perform debug commands. In some embodiments, an apparatus includes a processor core that includes path circuitry configured to access data for instructions executed by the processor core and storage elements which the path circuitry is configured to access via one or more ports. In some embodiments, the apparatus includes debug circuitry configured to receive external debug inputs and send abstract commands to the processor core based on the external debug inputs. In some embodiments, the apparatus includes control circuitry in the processor core configured to, in response to an abstract command to access one or more of the storage elements: generate signaling to access the one or more storage elements using the path circuitry, access read data from the one or more storage elements based on the signaling, and transmit the accessed read data to the debug circuitry.

Abstract: Techniques are disclosed relating to the handling of exceptions generated by illegal instructions in a processor. In an embodiment, a processor may be configured to fetch instructions defined according to an instruction set architecture (ISA). The ISA may include a set of uncompressed instructions and a set of compressed instructions. The processor may further be configured to, upon detecting a given one of the set of compressed instructions, cause a copy of the given compressed instruction to be saved and convert the given compressed instruction to a corresponding given uncompressed instruction. The processor may also be configured to detect that the given uncompressed instruction is illegal and was converted from the given compressed instruction, and based at least in part on these, cause an illegal instruction exception to be generated using the copy of the given compressed instruction.

Abstract: Techniques are disclosed relating to cache debug using control registers based on debug commands. In some embodiments, an apparatus includes a processor core, debug circuitry, and control circuitry. In some embodiments, the debug circuitry is configured to receive external debug inputs and send abstract commands to the processor core based on the external debug inputs. In some embodiments, the control circuitry is configured to, in response to an abstract command to read data from the cache: write cache address information to a first control register, assert a trigger signal to cause a read of the data from the cache to a second control register, based on the cache address information in the first control register, and send data from the second control register to the debug circuitry. In various embodiments, this may facilitate hardware cache debug using debug circuitry that also controls software debugging.

Abstract: Techniques are disclosed relating to the handling of exceptions generated by illegal instructions in a processor. In an embodiment, a processor may be configured to fetch instructions defined according to an instruction set architecture (ISA). The ISA may include a set of uncompressed instructions and a set of compressed instructions. The processor may further be configured to, upon detecting a given one of the set of compressed instructions, cause a copy of the given compressed instruction to be saved and convert the given compressed instruction to a corresponding given uncompressed instruction. The processor may also be configured to detect that the given uncompressed instruction is illegal and was converted from the given compressed instruction, and based at least in part on these, cause an illegal instruction exception to be generated using the copy of the given compressed instruction.

Abstract: Techniques are disclosed relating to using non-debug path circuitry to perform debug commands. In some embodiments, an apparatus includes a processor core that includes path circuitry configured to access data for instructions executed by the processor core and storage elements which the path circuitry is configured to access via one or more ports. In some embodiments, the apparatus includes debug circuitry configured to receive external debug inputs and send abstract commands to the processor core based on the external debug inputs.

Abstract: Techniques are disclosed relating to cache debug using control registers based on debug commands. In some embodiments, an apparatus includes a processor core, debug circuitry, and control circuitry. In some embodiments, the debug circuitry is configured to receive external debug inputs and send abstract commands to the processor core based on the external debug inputs. In some embodiments, the control circuitry is configured to, in response to an abstract command to read data from the cache: write cache address information to a first control register, assert a trigger signal to cause a read of the data from the cache to a second control register, based on the cache address information in the first control register, and send data from the second control register to the debug circuitry. In various embodiments, this may facilitate hardware cache debug using debug circuitry that also controls software debugging.

Abstract: Systems and methods for efficient out-of-order dynamic deallocation of entries within a shared storage resource in a processor. A processor comprises a unified pick queue that includes an array configured to dynamically allocate any entry of a plurality of entries for a decoded and renamed instruction. This instruction may correspond to any available active threads supported by the processor. The processor includes circuitry configured to determine whether an instruction corresponding to an allocated entry of the plurality of entries is dependent on a speculative instruction and whether the instruction has a fixed instruction execution latency. In response to determining the instruction is not dependent on a speculative instruction, the instruction has a fixed instruction execution latency, and said latency has transpired, the circuitry may deallocate the instruction from the allocated entry.

Abstract: Systems and methods for identification of dependent instructions on speculative load operations in a processor. A processor allocates entries of a unified pick queue for decoded and renamed instructions. Each entry of a corresponding dependency matrix is configured to store a dependency bit for each other instruction in the pick queue. The processor speculates that loads will hit in the data cache, hit in the TLB and not have a read after write (RAW) hazard. For each unresolved load, the pick queue tracks dependent instructions via dependency vectors based upon the dependency matrix. If a load speculation is found to be incorrect, dependent instructions in the pick queue are reset to allow for subsequent picking, and dependent instructions in flight are canceled. On completion of a load miss, dependent operations are re-issued. On resolution of a TLB miss or RAW hazard, the original load is replayed and dependent operations are issued again from the pick queue.

Abstract: Techniques are disclosed relating to integrated circuits that include hardware support for divide and/or square root operations. In one embodiment, an integrated circuit is disclosed that includes a division unit that, in turn, includes a normalization circuit and a plurality of divide engines. The normalization circuit is configured to normalize a set of operands. Each divide engine is configured to operate on a respective normalized set of operands received from the normalization circuit. In some embodiments, the integrated circuit includes a scheduler unit configured to select instructions for issuance to a plurality of execution units including the division unit. The scheduler unit is further configured to maintain a counter indicative of a number of instructions currently being operated on by the division unit, and to determine, based on the counter whether to schedule subsequent instructions for issuance to the division unit.

Abstract: Systems and methods for efficient picking of instructions for out-of-order issue and execution in a processor. In one embodiment, a processor comprises a unified pick queue that is dynamically allocated. Each entry is configured to store age and dependency information relative to other decoded instructions. Also, each entry stores a picked field, which when asserted indicates the decoded instruction has already been picked for out-of-order issue and execution. When asserted, a trigger field indicates a result of a corresponding decoded instruction will be available a predetermined number of clock cycles afterward. A younger instruction dependent on a result of an older instruction is ready to be picked before the result of the older instruction is available. In this case, the older instruction has asserted picked and trigger fields.

Abstract: Various techniques for mitigating dependencies between groups of instructions are disclosed. In one embodiment, such dependencies include “evil twin” conditions, in which a first floating-point instruction has as a destination a first portion of a logical floating-point register (e.g., a single-precision write), and in which a second, subsequent floating-point instruction has as a source the first portion and a second portion of the same logical floating-point register (e.g., a double-precision read). The disclosed techniques may be applicable in a multithreaded processor implementing register renaming. In one embodiment, a processor may enter an operating mode in which detection of evil twin “producers” (e.g., single-precision writes) causes the instruction sequence to be modified to break potential dependencies. Modification of the instruction sequence may continue until one or more exit criteria are reached (e.g., committing a predetermined number of single-precision writes).

Abstract: Techniques are disclosed relating to integrated circuits that include hardware support for divide and/or square root operations. In one embodiment, an integrated circuit is disclosed that includes a division unit that, in turn, includes a normalization circuit and a plurality of divide engines. The normalization circuit is configured to normalize a set of operands. Each divide engine is configured to operate on a respective normalized set of operands received from the normalization circuit. In some embodiments, the integrated circuit includes a scheduler unit configured to select instructions for issuance to a plurality of execution units including the division unit. The scheduler unit is further configured to maintain a counter indicative of a number of instructions currently being operated on by the division unit, and to determine, based on the counter whether to schedule subsequent instructions for issuance to the division unit.

Abstract: Systems and methods for efficient thread arbitration in a processor. A processor comprises a multi-threaded resource. The resource may include an array of entries which may be allocated by threads. A thread arbitration table corresponding to a given thread stores a high and a low threshold value in each table entry. A thread history shift register (HSR) indexes the table, wherein each bit of the HSR indicates whether the given thread is a thread hog. When the given thread has more allocated entries in the array than the high threshold of the table entry, the given thread is stalled from further allocating array entries. Similarly, when the given thread has fewer allocated entries in the array than the low threshold of the selected table entry, the given thread is permitted to allocate entries. In this manner, threads that hog dynamic resources can be mitigated such that more resources are available to other threads that are not thread hogs.