Patents by Inventor Matthew Bace

Matthew Bace has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • User level control of power management policies
    Patent number: 10372197
    Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: August 6, 2019
    Assignee: Intel Corporation
    Inventors: Krishnakanth V. Sistla, Jeremy Shrall, Stephen H. Gunther, Efraim Rotem, Alon Naveh, Eliezer Weissmann, Anil Aggarwal, Martin T. Rowland, Ankush Varma, Ian M. Steiner, Matthew Bace, Avinash N. Ananthakrishnan, Jason Brandt
  • Dynamically modifying a power/performance tradeoff based on a processor utilization
    Patent number: 9760409
    Abstract: In one embodiment, the present invention includes a multicore processor having a power controller with logic to dynamically switch a power management policy from a power biased policy to a performance biased policy when a utilization of the processor exceeds a threshold level. Thus at low utilizations, reduced power consumption can be realized, while at higher utilizations, greater performance can be realized. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: September 12, 2017
    Assignee: Intel Corporation
    Inventors: Krishnakanth V. Sistla, Mark Rowland, Ankush Varma, Ian M. Steiner, Matthew Bace, Daniel Borkowski, Vivek Garg, Chelsea Akturan, Avinash N. Ananthakrishnan
  • User Level Control Of Power Management Policies
    Publication number: 20170083076
    Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.
    Type: Application
    Filed: December 2, 2016
    Publication date: March 23, 2017
    Inventors: Krishnakanth V. Sistla, Jeremy Shrall, Stephen H. Gunther, Efraim Rotem, Alon Naveh, Eliezer Weissmann, Anil Aggarwal, Martin T. Rowland, Ankush Varma, Ian M. Steiner, Matthew Bace, Avinash N. Ananthakrishnan, Jason Brandt
  • User level control of power management policies
    Patent number: 9535487
    Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: January 3, 2017
    Assignee: Intel Corporation
    Inventors: Krishnakanth V. Sistla, Jeremy Shrall, Stephen H. Gunther, Efraim Rotem, Alon Naveh, Eliezer Weissmann, Anil Aggarwal, Martin T. Rowland, Ankush Varma, Ian M. Steiner, Matthew Bace, Avinash N. Ananthakrishnan, Jason Brandt
  • Dynamically Modifying A Power/Performance Tradeoff Based On A Processor Utilization
    Publication number: 20160266941
    Abstract: In one embodiment, the present invention includes a multicore processor having a power controller with logic to dynamically switch a power management policy from a power biased policy to a performance biased policy when a utilization of the processor exceeds a threshold level. Thus at low utilizations, reduced power consumption can be realized, while at higher utilizations, greater performance can be realized. Other embodiments are described and claimed.
    Type: Application
    Filed: May 24, 2016
    Publication date: September 15, 2016
    Inventors: Krishnakanth V. Sistla, Mark Rowland, Ankush Varma, Ian M. Steiner, Matthew Bace, Daniel Borkowski, Vivek Garg, Cagdas Akturan, Avinash N. Ananthakrishnan
  • Adaptively limiting a maximum operating frequency in a multicore processor
    Patent number: 9377841
    Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, and a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a control logic to reduce a maximum operating frequency of the processor if a first number of forced performance state transitions occurs in a first time period or a second number of forced performance state transitions occurs in a second time period. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 8, 2013
    Date of Patent: June 28, 2016
    Assignee: Intel Corporation
    Inventors: Ankush Varma, Ian Steiner, Avinash Ananthakrishnan, Krishnakanth Sistla, Chris Poirier, Matthew Bace, Eric Dehaemer
  • Dynamically modifying a power/performance tradeoff based on processor utilization
    Patent number: 9372524
    Abstract: In one embodiment, the present invention includes a multicore processor having a power controller with logic to dynamically switch a power management policy from a power biased policy to a performance biased policy when a utilization of the processor exceeds a threshold level. Thus at low utilizations, reduced power consumption can be realized, while at higher utilizations, greater performance can be realized. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: June 21, 2016
    Assignee: Intel Corporation
    Inventors: Krishnakanth V. Sistla, Mark Rowland, Ankush Varma, Ian M. Steiner, Matthew Bace, Daniel Borkowski, Vivek Garg, Cagdas Akturan, Avinash N. Ananthakrishnan
  • User Level Control Of Power Management Policies
    Publication number: 20160004291
    Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.
    Type: Application
    Filed: September 16, 2015
    Publication date: January 7, 2016
    Inventors: Krishnakanth V. Sistla, Jeremy Shrall, Stephen H. Gunther, Efraim Rotem, Alon Naveh, Eliezer Weissmann, Anil Aggarwal, Martin T. Rowland, Ankush Varma, Ian M. Steiner, Matthew Bace, Avinash N. Ananthakrishnan, Jason Brandt
  • User level control of power management policies
    Patent number: 9170624
    Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: October 27, 2015
    Assignee: Intel Corporation
    Inventors: Krishnakanth V. Sistla, Jeremy Shrall, Stephen H. Gunther, Efraim Rotem, Alon Naveh, Eliezer Weissmann, Anil Aggarwal, Martin T. Rowland, Ankush Varma, Ian M. Steiner, Matthew Bace, Avinash N. Ananthakrishnan, Jason Brandt
  • User level control of power management policies
    Patent number: 9098261
    Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: August 4, 2015
    Assignee: Intel Corporation
    Inventors: Krishnakanth V. Sistla, Jeremy Shrall, Stephen H. Gunther, Efraim Rotem, Alon Naveh, Eliezer Weissmann, Anil Aggarwal, Martin T. Rowland, Ankush Varma, Ian M. Steiner, Matthew Bace, Avinash N. Ananthakrishnan, Jason Brandt
  • Adaptively Limiting A Maximum Operating Frequency In A Multicore Processor
    Publication number: 20140337646
    Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, and a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a control logic to reduce a maximum operating frequency of the processor if a first number of forced performance state transitions occurs in a first time period or a second number of forced performance state transitions occurs in a second time period. Other embodiments are described and claimed.
    Type: Application
    Filed: May 8, 2013
    Publication date: November 13, 2014
    Inventors: ANKUSH VARMA, IAN STEINER, AVINASH ANANTHAKRISHNAN, KRISHNAKANTH SISTLA, CHRIS POIRIER, MATTHEW BACE, ERIC DEHAEMER
  • User Level Control Of Power Management Policies
    Publication number: 20130179706
    Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.
    Type: Application
    Filed: March 1, 2013
    Publication date: July 11, 2013
    Inventors: Krishnakanth V. Sistla, Jeremy Shrall, Stephen H. Gunther, Efraim Rotem, Alon Naveh, Eliezer Weissmann, Anil Aggarwal, Martin T. Rowland, Ankush Varma, Ian M. Steiner, Matthew Bace, Avinash N. Ananthakrishnan, Jason Brandt
  • User Level Control Of Power Management Policies
    Publication number: 20120204042
    Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.
    Type: Application
    Filed: December 15, 2011
    Publication date: August 9, 2012
    Inventors: Krishnakanth V. Sistla, Jeremy Shrall, Stephen H. Gunther, Efraim Rotem, Alon Naveh, Eliezer Weissmann, Anil Aggarwal, Martin T. Rowland, Ankush Varma, Ian M. Steiner, Matthew Bace, Avinash N. Ananthakrishnan, Jason Brandt
  • Dynamically Modifying A Power/Performance Tradeoff Based On Processor Utilization
    Publication number: 20120144217
    Abstract: In one embodiment, the present invention includes a multicore processor having a power controller with logic to dynamically switch a power management policy from a power biased policy to a performance biased policy when a utilization of the processor exceeds a threshold level. Thus at low utilizations, reduced power consumption can be realized, while at higher utilizations, greater performance can be realized. Other embodiments are described and claimed.
    Type: Application
    Filed: December 15, 2011
    Publication date: June 7, 2012
    Inventors: Krishnakanth V. Sistla, Mark Rowland, Ankush Varma, Ian M. Steiner, Matthew Bace, Daniel Borkowski, Vivek Garg, Cagdas Akturan, Avinash N. Ananthakrishnan
  • Cipher block chaining decryption
    Publication number: 20050053232
    Abstract: According to some embodiments, cipher block chaining decryption is performed.
    Type: Application
    Filed: September 4, 2003
    Publication date: March 10, 2005
    Inventor: Matthew Bace