Patents by Inventor Matthew Barlow

Matthew Barlow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11838021
    Abstract: An improved electrical circuit for logic output level shifting using SiC JFETs with resistors on the input, inverting, stage and using diode degenerated JFET sources in the output stage.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: December 5, 2023
    Inventors: Matthew Barlow, James A. Holmes
  • Patent number: 11647582
    Abstract: A multi-layer ceramic wiring board is patterned with arrays of footprints for high-temperature surface mounted device active and passive components on one side of the board that is patterned with arrays of standard SMD footprints to enable placement and attachment of components including primary 2-terminal components and active components where the SMD pads are connected through vias and buried-layer interconnect traces to a multiple connection point arrays on the front and back side of the ceramic wiring board. Each pad is connected to multiple instances of the pad grid to connections to be made with a single post-fired print.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: May 9, 2023
    Inventors: Ian Getreu, James A. Holmes, Brandon Dyer, Jacob Kupernik, Matthew Barlow, Nicholas Chiolino, Anthony Matt Francis
  • Patent number: 11251717
    Abstract: An integrated silicon carbide rectifier circuit with an on chip isolation diode. The isolation diode can be a channel-to-substrate isolation diode or a channel to channel isolation diode. the circuit teaches an integrated diode rectification circuit for use with a two phase center tap transformer having a first voltage output, a second voltage output, and a center tap output with a single chip having a first half-wave rectifier connected to the first voltage output, a second half-wave rectifier connected to the second voltage output, and a floating substrate connection connected to the center tap output and an on chip first channel-to-substrate isolation diode electrically connected between the first half-wave rectifier and the floating substrate.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: February 15, 2022
    Inventors: Matthew Barlow, James A. Holmes
  • Patent number: 10720853
    Abstract: An integrated silicon carbide rectifier circuit with an on chip isolation diode. The isolation diode can be a channel-to-substrate isolation diode or a channel to channel isolation diode.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: July 21, 2020
    Inventors: Matthew Barlow, James A. Holmes
  • Patent number: 10608636
    Abstract: An improved electrical circuit for logic output level shifting using SiC JFETs with resistors on the input, inverting, stage and using diode degenerated JFET sources in the output stage.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: March 31, 2020
    Inventors: Matthew Barlow, James A. Holmes