Abstract: An n-bit prefix tree adder includes n prefix trees, each associated with a bit position of the adder and including a number of computation stages. In accordance with an illustrative embodiment of the invention, the prefix trees are interconnected such that carry signals are computed at least partially in parallel. For example, a carry signal computed in an initial stage of a given prefix tree is used in subsequent stages of the given prefix tree without introducing substantial additional delay in computation of other carry signals in other prefix trees associated with higher bit positions. Carries computed for lower bit positions are thus used to compute carries for higher bit positions, but generate, propagate and/or transmit signals may be generated in an initial stage of each of the prefix trees without utilizing a primary carry input signal in the computation. The resulting adder architecture provides reduced logic depth, delay and circuit area relative to conventional architectures.