Patents by Inventor Matthew Breitwisch
Matthew Breitwisch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8189372Abstract: An integrated circuit includes a first electrode including an etched recessed portion. The integrated circuit includes a second electrode and a resistivity changing material filling the recessed portion and coupled to the second electrode.Type: GrantFiled: February 5, 2008Date of Patent: May 29, 2012Assignees: International Business Machines Corporation, Macronix International Co., Ltd., Qimonda AGInventors: Matthew Breitwisch, Shihhung Chen, Thomas Happ, Eric Joseph
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Patent number: 7910911Abstract: An embodiment of the present invention includes a phase change memory (PCM) structure configurable for use as a nonvolatile storage element. The element includes at least one bottom electrode; at least one phase change material layer on at least a portion of an upper surface of the bottom electrode; and at least one heater layer on at least a portion of an upper surface of the phase change material layer, wherein the heater layer has a tapered shape such that an upper surface of the heater layer has a cross-sectional width that is longer than a cross-sectional width of a bottom surface of the heater layer contacting the phase change material layer.Type: GrantFiled: July 29, 2009Date of Patent: March 22, 2011Assignee: International Business Machines CorporationInventors: Matthew Breitwisch, Thomas Happ, Eric A. Joseph, Hsiang-Lan Lung, Jan Boris Philipp
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Patent number: 7906368Abstract: An embodiment of the present invention includes a method of forming a nonvolatile phase change memory (PCM) cell. This method includes forming at least one bottom electrode; forming at least one phase change material layer on at least a portion of an upper surface of the bottom electrode; forming at least one heater layer on at least a portion of an upper surface of the phase change material layer; and shaping the heater layer into a tapered shape, such that an upper surface of the heater layer has a cross-sectional width that is longer than a cross-sectional width of a bottom surface of the heater layer contacting the phase change material layer.Type: GrantFiled: June 29, 2007Date of Patent: March 15, 2011Assignee: International Business Machines CorporationInventors: Matthew Breitwisch, Thomas Happ, Eric A. Joseph, Hsiang-Lan Lung, Jan Boris Philipp
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Publication number: 20090289242Abstract: An embodiment of the present invention includes a method of forming a nonvolatile phase change memory (PCM) cell. This method includes forming at least one bottom electrode; forming at least one phase change material layer on at least a portion of an upper surface of the bottom electrode; forming at least one heater layer on at least a portion of an upper surface of the phase change material layer; and shaping the heater layer into a tapered shape, such that an upper surface of the heater layer has a cross-sectional width that is longer than a cross-sectional width of a bottom surface of the heater layer contacting the phase change material layer. Another embodiment of the present invention includes a phase change memory (PCM) structure configurable for use as a nonvolatile storage element.Type: ApplicationFiled: July 29, 2009Publication date: November 26, 2009Applicant: International Business Machines CorporationInventors: Matthew Breitwisch, Thomas Happ, Eric A. Joseph, Hsiang-Lan Lung, Jan Boris Philipp
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Publication number: 20090196094Abstract: An integrated circuit includes a first electrode including an etched recessed portion. The integrated circuit includes a second electrode and a resistivity changing material filling the recessed portion and coupled to the second electrode.Type: ApplicationFiled: February 5, 2008Publication date: August 6, 2009Inventors: Matthew Breitwisch, Shihhung Chen, Thomas Happ, Eric Joseph
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Publication number: 20090001341Abstract: An embodiment of the present invention includes a method of forming a nonvolatile phase change memory (PCM) cell. This method includes forming at least one bottom electrode; forming at least one phase change material layer on at least a portion of an upper surface of the bottom electrode; forming at least one heater layer on at least a portion of an upper surface of the phase change material layer; and shaping the heater layer into a tapered shape, such that an upper surface of the heater layer has a cross-sectional width that is longer than a cross-sectional width of a bottom surface of the heater layer contacting the phase change material layer. Another embodiment of the present invention includes a phase change memory (PCM) structure configurable for use as a nonvolatile storage element.Type: ApplicationFiled: June 29, 2007Publication date: January 1, 2009Inventors: Matthew Breitwisch, Thomas Happ, Eric A. Joseph, Hsiang-Lan Lung, Jan Boris Philipp
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Patent number: 7378710Abstract: An integrated circuit, such as a SRAM cell (130), including an inverted FinFET transistor (P2) and a FinFET transistor (N3). The inverted FinFET transistor includes a first gate region (108) formed by semiconductor structure (100) on a substrate, a first body region comprised of a semiconductor layer (104), having a first channel region (112) disposed on the first gate region and a source (110) and drain (114) formed on either side of the first channel region. The FinFET transistor (N3) is coupled to the inverted FinFET transistor, and includes a second body region formed by the semiconductor structure (102), having a second channel region (118), and a source (116) and drain (120) formed on either side of the second channel region, and a second gate region (122) comprised of the semiconductor layer, disposed on the second channel region.Type: GrantFiled: December 19, 2002Date of Patent: May 27, 2008Assignee: International Business Machines CorporationInventors: Matthew Breitwisch, Edward J. Nowak
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Publication number: 20070246748Abstract: A memory cell comprises a dielectric layer and a phase change material. The dielectric layer defines a trench having both a wide portion and a narrow portion. The narrow portion is substantially narrower than the wide portion. The phase change material, in turn, at least partially fills the wide and narrow portions of the trench. What is more, the phase change material within the narrow portion of the trench defines a void. Data can be stored in the memory cell by heating the phase change material by applying a pulse of switching current to the memory cell. Advantageously, embodiments of the invention provide high switching current density and heating efficiency so that the magnitude of the switching current pulse can be reduced.Type: ApplicationFiled: April 25, 2006Publication date: October 25, 2007Inventors: Matthew Breitwisch, Chung Lam, Jan Philipp, Stephen Rossnagel, Alejandro Schrott
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Publication number: 20070201267Abstract: A memory includes a phase-change memory cell and a circuit. The phase-change memory cell can be set to at least three different states including a substantially crystalline state, a substantially amorphous state, and at least one partially crystalline and partially amorphous state. The circuit applies a first voltage across the memory cell to determine whether the memory cell is set at the substantially crystalline state and applies a second voltage across the memory cell to determine whether the memory cell is set at a partially crystalline and partially amorphous state.Type: ApplicationFiled: February 24, 2006Publication date: August 30, 2007Inventors: Thomas Happ, Matthew Breitwisch, Hsiang-Lang Lung
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Publication number: 20070128776Abstract: The present invention provides a method of forming an ultra-thin and uniform layer of Si including the steps of providing a substrate having semiconducting regions separated by insulating regions; implanting dopants into the substrate to provide an etch differential doped portion in the semiconducting regions underlying an upper Si-containing surface of the semiconducting regions; forming a trench in the substrate including the semiconducting regions and the insulating regions; removing the etch differential doped portion from the semiconductor regions to produce a cavity underlying the upper surface of the semiconducting regions; and filling the trench with a trench dielectric, wherein the trench dielectric material encloses the cavity underlying the upper Si-containing surface of the semiconducting regions. The upper Si-containing surface of the semiconducting regions has a uniform thickness of less than about 100 ?.Type: ApplicationFiled: February 1, 2007Publication date: June 7, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew Breitwisch, Chung Lam, Randy Mann, Dale Martin
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Publication number: 20070023756Abstract: A field effect transistor (FET) and method of forming the FET comprises a substrate; a silicon germanium (SiGe) layer over the substrate; a semiconductor layer over and adjacent to the SiGe layer; an insulating layer adjacent to the substrate, the SiGe layer, and the semiconductor layer; a pair of first gate structures adjacent to the insulating layer; and a second gate structure over the insulating layer. Preferably, the insulating layer is adjacent to a side surface of the SiGe layer and an upper surface of the semiconductor layer, a lower surface of the semiconductor layer, and a side surface of the semiconductor layer. Preferably, the SiGe layer comprises carbon. Preferably, the pair of first gate structures are substantially transverse to the second gate structure. Additionally, the pair of first gate structures are preferably encapsulated by the insulating layer.Type: ApplicationFiled: July 27, 2005Publication date: February 1, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brent Anderson, Matthew Breitwisch, Edward Nowak, BethAnn Rainey
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Publication number: 20060286724Abstract: Disclosed is a tri-gate field effect transistor with a back gate and the associated methods of forming the transistor. Specifically, a back gate is incorporated into a lower portion of a fin. A tri-gate structure is formed on the fin and is electrically isolated from the back gate. The back gate can be used to control the threshold voltage of the FET. In one embodiment the back gate extends to an n-well in a p-type silicon substrate. A contact to the n-well allows electrical voltage to be applied to the back gate. A diode created between the n-well and p-substrate isolates the current flowing through the n-well from other devices on the substrate so that the back gate can be independently biased. In another embodiment the back gate extends to n-type polysilicon layer on an insulator layer on a p-type silicon substrate. A contact to the n-type polysilicon layer allows electrical voltage to be applied to the back gate.Type: ApplicationFiled: June 21, 2005Publication date: December 21, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brent Anderson, Matthew Breitwisch, Edward Nowak
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Patent number: 7123517Abstract: A reprogrammable integrated circuit (IC) including overwritable nonvolatile storage cells. Cell contents are compared in a differential sense amplifier against a variable reference signal that has a number of selectable reference levels corresponding to reprogrammed cell threshold voltages. With each write cycle the nonvolatile storage cells are overwritten and then, compared against a different, e.g., higher, selectable reference level.Type: GrantFiled: October 7, 2004Date of Patent: October 17, 2006Assignee: International Business Machines CorporationInventors: Matthew Breitwisch, Chung H. Lam, Steven Mittl, Jian W. Zhu
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Publication number: 20060077719Abstract: A reprogrammable integrated circuit (IC) including overwritable nonvolatile storage cells. Cell contents are compared in a differential sense amplifier against a variable reference signal that has a number of selectable reference levels corresponding to reprogrammed cell threshold voltages. With each write cycle the nonvolatile storage cells are overwritten and then, compared against a different, e.g., higher, selectable reference level.Type: ApplicationFiled: October 7, 2004Publication date: April 13, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew Breitwisch, Chung Lam, Steven Mittl, Jian Zhu
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Publication number: 20060068531Abstract: An integrated circuit, such as a SRAM cell (130), including an inverted FinFET transistor (P2) and a FinFET transistor (N3). The inverted FinFET transistor includes a first gate region (108) formed by semiconductor structure (100) on a substrate, a first body region comprised of a semiconductor layer (104), having a first channel region (112) disposed on the first gate region and a source (110) and drain (114) formed on either side of the first channel region. The FinFET transistor (N3) is coupled to the inverted FinFET transistor, and includes a second body region formed by the semiconductor structure (102), having a second channel region (118), and a source (116) and drain (120) formed on either side of the second channel region, and a second gate region (122) comprised of the semiconductor layer, disposed on the second channel region.Type: ApplicationFiled: December 19, 2002Publication date: March 30, 2006Inventors: Matthew Breitwisch, Edward Nowak
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Publication number: 20060027889Abstract: The present invention provides a method of forming an ultra-thin and uniform layer of Si including the steps of providing a substrate having semiconducting regions separated by insulating regions; implanting dopants into the substrate to provide an etch differential doped portion in the semiconducting regions underlying an upper Si-containing surface of the semiconducting regions; forming a trench in the substrate including the semiconducting regions and the insulating regions; removing the etch differential doped portion from the semiconductor regions to produce a cavity underlying the upper surface of the semiconducting regions; and filling the trench with a trench dielectric, wherein the trench dielectric material encloses the cavity underlying the upper Si-containing surface of the semiconducting regions. The upper Si-containing surface of the semiconducting regions has a uniform thickness of less than about 100 ?.Type: ApplicationFiled: August 5, 2004Publication date: February 9, 2006Applicant: International Business Machines CorporationInventors: Matthew Breitwisch, Chung Lam, Randy Mann, Dale Martin