Abstract: A system for configuring a storage area network (SAN) may include a plurality of selectable SAN elements, and a design module operable to graphically configure selected SAN elements, and a validation engine operable to dynamically validate the configuration of the selected SAN elements. The validation engine may include an element related validation module and a group related validation module. The element related validation module may be configured to validate element to element relationships of connected SAN elements in the configuration of selected SAN elements. The group related validation module may be configured to validate a group of SAN elements in the configuration of selected SAN elements. The validation modules may be arranged such that during validation of the configuration of selected SAN elements, the element related validation module is employed before the group related validation module.

Abstract: A system and method is disclosed for the implementation of a common descriptor format for storage data formats regardless of the storage media. An example storage medium using a common descriptor format may comprise data stored on the storage medium and a common descriptor that is associated with the stored data and stored on the storage medium. The common descriptor may include formatting information stored in a standardized format. The formatting information may be sufficient to describe how the data is formatted.

Abstract: A system for detecting and reporting memory errors in error correctable memory in a computer system includes a chipset that utilizes the error correctable memory for creating an error detection signal when a memory error occurs. The error detection signal includes data that may be utilized to identify the error correctable memory having a memory error. The system further includes a motherboard having two or more memory interface slots, where the error correctable memory is coupled with at least one of the interface slots, and each of the at least one slots has a unique slot identification number. The chipset is coupled to the motherboard, and the system further includes a driver coupled to the chipset. The motherboard has at least one register that receives the error detection signal and stores the data in the error detection signal in the at least one register.