Abstract: Transport Layer Security (TLS) connection establishment between a client and a server for a new session is enabled using an ephemeral (temporary) key pair. In response to a request, the server generates a temporary certificate by signing an ephemeral public key using the server's private key. A certificate chain comprising at least the temporary certificate that includes the ephemeral public key, together with a server certificate, is output to the client by the server, which acts as a subordinate Certificate Authority. The client validates the certificates, generates a session key and outputs the session key wrapped by the ephemeral public key. To complete the connection establishment, the server applies the ephemeral private key to recover the session key derived at the client for the new session. The client and server thereafter use the session key to encrypt and decrypt data over the link. The ephemeral key pair is not reused.

Abstract: One embodiment of the present invention includes techniques to decrease power consumption by reducing the number of redundant operations performed. In operation, a streamlining multiprocessor (SM) identifies uniform groups of threads that, when executed, apply the same deterministic operation to uniform sets of input operands. Within each uniform group of threads, the SM designates one thread as the anchor thread. The SM disables execution units assigned to all of the threads except the anchor thread. The anchor execution unit, assigned to the anchor thread, executes the operation on the uniform set of input operands. Subsequently, the SM sets the outputs of the non-anchor threads included in the uniform group of threads to equal the value of the anchor execution unit output.

Abstract: A method, computer readable medium, and system are disclosed for performing spatiotemporal filtering. The method includes the steps of applying, utilizing a processor, a temporal filter of a filtering pipeline to a current image frame, using a temporal reprojection, to obtain a color and auxiliary information for each pixel within the current image frame, providing the auxiliary information for each pixel within the current image frame to one or more subsequent filters of the filtering pipeline, and creating a reconstructed image for the current image frame, utilizing the one or more subsequent filters of the filtering pipeline.

Abstract: A subsystem is configured to support a distributed instruction set architecture with primary and secondary execution pipelines. The primary execution pipeline supports the execution of a subset of instructions in the distributed instruction set architecture that are issued frequently. The secondary execution pipeline supports the execution of another subset of instructions in the distributed instruction set architecture that are issued less frequently. Both execution pipelines also support the execution of FFMA instructions as well as a common subset of instructions in the distributed instruction set architecture. When dispatching a requested instruction, an instruction scheduling unit is configured to select between the two execution pipelines based on various criteria. Those criteria may include power efficiency with which the instruction can be executed and availability of execution units to support execution of the instruction.

Abstract: A personalized score for a place that a user may want to visit is computed and displayed to the user. The score is computed based on at least one of inferred or explicit parameters, using machine learning. The score may be displayed to the user in connection with the place, and in some examples explanations of the underlying factors that resulted in the score are also displayed. Because each user is unique, the score may be different for one person than for another. Accordingly, when a group of friends are deciding on a place to visit, such as a place to eat, the personalized score for a given restaurant may be higher for a first user than for a second user.

Abstract: A modular exciter beam fitted to a vibratory screen assembly. The exciter beam spans between opposing side walls of the screen assembly. The modular exciter beam provides mounting for a pair of exciter mechanisms which are located substantially inside the side walls of the screen assembly.

Abstract: A method, computer readable medium, and system are disclosed for performing spatiotemporal filtering. The method includes the steps of applying, utilizing a processor, a temporal filter of a filtering pipeline to a current image frame, using a temporal reprojection, to obtain a color and auxiliary information for each pixel within the current image frame, providing the auxiliary information for each pixel within the current image frame to one or more subsequent filters of the filtering pipeline, and creating a reconstructed image for the current image frame, utilizing the one or more subsequent filters of the filtering pipeline.

Abstract: A modular exciter beam fitted to a vibratory screen assembly. The exciter beam spans between opposing side walls of the screen assembly. The modular exciter beam provides mounting for a pair of exciter mechanisms which are located substantially inside the side walls of the screen assembly.

Abstract: A reconstitution device having an opening surrounded by a neck, and a cap including a first end, a second end, and an inner bore having a central aperture. A stopper is positioned in the opening of the neck and includes a portion capable of being perforated. A plunger is located at the second end of the cap, is configured to slide along the inner bore of the cap, and includes a shaft extending downwardly in a direction towards the stopper and having a pointed end for piercing the stopper. A locking mechanism is located in the cap and includes an aperture. The locking mechanism is configured such that when the plunger is pushed downwardly the shaft is allowed to pass through the aperture, but when the plunger is pulled upwardly the second aperture changes shape such that the shaft cannot freely pass through the aperture.

Abstract: A subsystem is configured to support a distributed instruction set architecture with primary and secondary execution pipelines. The primary execution pipeline supports the execution of a subset of instructions in the distributed instruction set architecture that are issued frequently. The secondary execution pipeline supports the execution of another subset of instructions in the distributed instruction set architecture that are issued less frequently. Both execution pipelines also support the execution of FFMA instructions as well a common subset of instructions in the distributed instruction set architecture. When dispatching a requested instruction, an instruction scheduling unit is configured to select between the two execution pipelines based on various criteria. Those criteria may include power efficiency with which the instruction can be executed and availability of execution units to support execution of the instruction.

Abstract: One embodiment of the present invention includes techniques to decrease power consumption by reducing the number of redundant operations performed. In operation, a streamlining multiprocessor (SM) identifies uniform groups of threads that, when executed, apply the same deterministic operation to uniform sets of input operands. Within each uniform group of threads, the SM designates one thread as the anchor thread. The SM disables execution units assigned to all of the threads except the anchor thread. The anchor execution unit, assigned to the anchor thread, executes the operation on the uniform set of input operands. Subsequently, the SM sets the outputs of the non-anchor threads included in the uniform group of threads to equal the value of the anchor execution unit output. Advantageously, by exploiting the uniformity of data to reduce the number of execution units that execute, the SM dramatically reduces the power consumption compared to conventional SMs.

Abstract: A reconstitution device having an opening surrounded by a neck, and a cap including a first end, a second end, and an inner bore having a central aperture. A stopper is positioned in the opening of the neck and includes a portion capable of being perforated. A plunger is located at the second end of the cap, is configured to slide along the inner bore of the cap, and includes a shaft extending downwardly in a direction towards the stopper and having a pointed end for piercing the stopper. A locking mechanism is located in the cap and includes an aperture. The locking mechanism is configured such that when the plunger is pushed downwardly the shaft is allowed to pass through the aperture, but when the plunger is pulled upwardly the second aperture changes shape such that the shaft cannot freely pass through the aperture.

Abstract: A system and method are described for dynamically changing the size of a computer memory such as level 2 cache as used in a graphics processing unit. In an embodiment, a relatively large cache memory can be implemented in a computing system so as to meet the needs of memory intensive applications. But where cache utilization is reduced, the capacity of the cache can be reduced. In this way, power consumption is reduced by powering down a portion of the cache.

Abstract: A reconstitution device for storing a first component of a pharmaceutical preparation includes a receptacle, a cap having a first end secured to the receptacle, a second end, and an inner bore having a central aperture. The device further includes a stopper located between the receptacle and the cap, the stopper including a portion capable of being perforated. The device also includes a plunger secured to the second end of the cap, a locking mechanism located in the cap, and an actuating mechanism. The actuating mechanism may prevent the device from inadvertent activation.

Abstract: A system and method for performing zero-bandwidth-clears reduces external memory accesses by a graphics processor when performing clears and subsequent read operations. A set of clear values is stored in the graphics processor. Each region of a color or z buffer may be configured using a zero-bandwidth-clear command to reference a clear value without writing the external memory. The clear value is provided to a requestor without accessing the external memory when a read access is performed.

Abstract: A processor buffers asynchronous threads. Instructions requiring operations provided by a plurality of execution units are divided into phases, each phase having at least one computation operation and at least one memory access operation. Instructions within each phase are qualified and prioritized. The instructions may be qualified based on the status of the execution unit needed to execute one or more of the current instructions. The instructions may also be qualified based on an age of each instruction, status of the execution units, a divergence potential, locality, thread diversity, and resource requirements. Qualified instructions may be prioritized based on execution units needed to execute instructions and the execution units in use. One or more of the prioritized instructions is issued per cycle to the plurality of execution units.

Abstract: A reconstitution device for storing a first component of a pharmaceutical preparation includes a receptacle, a cap having a first end secured to the receptacle, a second end, and an inner bore having a central aperture. The device further includes a stopper located between the receptacle and the cap, the stopper including a portion capable of being perforated. The device also includes a plunger secured to the second end of the cap, a locking mechanism located in the cap, and an actuating mechanism. The actuating mechanism may prevent the device from inadvertent activation.

Abstract: A processor buffers asynchronous threads. Current instructions requiring operations provided by a plurality of execution units are divided into phases, each phase having at least one math operation and at least one texture cache access operation. Instructions within each phase are qualified and prioritized, with texture cache access operations in a subsequent phase not qualified until all of the texture cache access operations in a current phase have completed. The instructions may be qualified based on the status of the execution unit needed to execute one or more of the instructions. The instructions may also be qualified based on an age of each instruction, a divergence potential, locality, thread diversity, and resource requirements. Qualified instructions may be prioritized based on execution units needed to execute current instructions and the execution units in use. One or more of the prioritized instructions is issued per cycle to the plurality of execution units.