Abstract: A system and method for the fault simulation testing of circuits by using a behavioral model is provided. The behavioral model includes a fault bus, decoder, and input and output ports. The decoder decodes mapping fault values, which are applied to the fault bus, to either a no-fault or to a specific fault which is internally encoded into the behavioral model. Accordingly, a single behavioral model can be used to dynamically model a fault-free circuit or machine and one or more faulty circuits or machines based on the mapping fault data applied to each model's fault bus. A fault simulation tool applies test simulation data having mapping fault and test parameter data to at least two identically coded behavioral models (i.e., a fault-free model and a faulty model, as defined by the applied mapping fault data). Output data are generated by each behavioral model and recorded by the fault simulation tool.

Abstract: An improved logic simulation machine in which non-unitary delays of logic functions being simulated are permitted and in which the delay time can be made different for low-to-high and high-to-low transitions. A plurality of basic processors are interconnected with a control processor through an inter-processor switch. The logic functions being simulated are divided among the various basic processors. The control processor provides primary input data and communicates the results computed by the basic processors with other ones of the basic processors as needed. All of the basic processors and the control processor operate in variable length work cycles. The length of a work cycle is determined by a minimum work space value among all of the logic functions to be simulated, that is, a minimum time to a next successive transition in a simulated output among all of the simulated logic functions. Further, the presence of glitches in the simulated output is detected.

Abstract: Disclosed is a memory cell circuit for a gate array. The memory cell circuit is D.C. testable and has particular utility when employed in an integrated circuit containing "a mix of logic and array".Also disclosed is a memory array particularly adapted for use in an integrated circuit containing TTL logic circuits.

Abstract: A test system for testing circuits in integrated circuit chips includes a host computer for controlling the test system, and a plurality of blocks operable in parallel and each including a controller, storage for test programs and test data, and plurality of electronic units or pin electronics cards, one unit being associated with one of the pins of a device under test. Each of the electronic units include timing circuitry for timing its associated pin independent of the timing of any other electronics unit.

Abstract: Disclosed is a design discipline, or approach, in the form of circuitry and a test method, or methodology which obviates the problems of the prior art and allows testing of each individual chip and interchip connections of a plurality of interconnected chips contained on or within a high density packaging structure. This testing is accomplished without the need for and utilization of test equipment having a precision probe and a high precision step and repeat mechanism. CPA is a method and circuit design discipline that, where followed, will result in a testable multichip package given that each logical component is testable and the design is synchronous in nature. The CPA discipline is able to accomplish this by making use of shift register latches on the chips or functional island periphery. These latches are used to indirectly observe and/or control the synchronous network, in many ways replicating the stuckfault test environment under which tests were generated at the lower subcomponent level of assembly.

Abstract: Disclosed is a design discipline, or approach, in the form of circuitry and a test method, or methodology which obviates the problems of the prior art and allows testing of each individual chip and interchip connections of a plurality of interconnected chips contained on or within a high density packaging structure. This testing is accomplished without the need for and utilization of test equipment having a precision probe and a high precision step and repeat mechanism. CPA is a method and circuit design discipline that, where followed, will result in a testable multichip package given that each logical component is testable and the design is synchronous in nature. The CPA discipline is able to accomplish this by making use of shift register latches on the chips or functional island periphery. These latches are used to indirectly observe and/or control the synchronous network, in many ways replicating the stuckfault test environment under which tests were generated at the lower subcomponent level of assembly.