Patents by Inventor Matthew C. Lanahan

Matthew C. Lanahan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8649239
    Abstract: Disclosed are embodiments of a multi-bank random access memory (RAM) structure that provides signal buffering at both the global and local connector level for improved performance. Specifically, inverters are incorporated into the global connector(s), which traverse groups of memory banks and which transmit signals (e.g., address signals, control signals, and/or data signals) from a memory controller, and also into alternating groups of local connectors, which connect nodes on the global connector(s) to corresponding groups of memory banks, such that any of the signals that are received by the memory banks from the memory controller via the global and local connectors are buffered by an even number of inverters and are thereby true signals. Signal buffering at both the global and local connector level results in relatively fast slews, short propagation delays, and low peak power consumption with minimal, if any, increase in area consumption.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: February 11, 2014
    Assignee: International Business Machines Corporation
    Inventors: Darren L. Anand, John A. Fifield, Mark D. Jacunski, Matthew C. Lanahan
  • Publication number: 20130315022
    Abstract: Disclosed are embodiments of a multi-bank random access memory (RAM) structure that provides signal buffering at both the global and local connector level for improved performance. Specifically, inverters are incorporated into the global connector(s), which traverse groups of memory banks and which transmit signals (e.g., address signals, control signals, and/or data signals) from a memory controller, and also into alternating groups of local connectors, which connect nodes on the global connector(s) to corresponding groups of memory banks, such that any of the signals that are received by the memory banks from the memory controller via the global and local connectors are buffered by an even number of inverters and are thereby true signals. Signal buffering at both the global and local connector level results in relatively fast slews, short propagation delays, and low peak power consumption with minimal, if any, increase in area consumption.
    Type: Application
    Filed: May 24, 2012
    Publication date: November 28, 2013
    Applicant: International Business Machines Corporation
    Inventors: Darren L. Anand, John A. Fifield, Mark D. Jacunski, Matthew C. Lanahan