Abstract: The present invention provides photolithographic device and method for photolithography process window. The photolithography device comprises a substrate; and a pattern layer having radiant energy transparent portions and radiant energy blocking portions, where the pattern layer has features with a varying overlay. The overlay tolerance is determined by varying the misalignment the features of the pattern. The photolithography device is a reticle. The method for determining an optimum photolithography process window comprises exposing a portion of a wafer to a pattern produced by a reticle, the pattern having a varying overlay that produces multiple photolithography conditions, wherein each photolithography condition has an overlay tolerance; and stepping the reticle across a remaining portion of the wafer, where each step exposes an other region of the wafer to the pattern producing multiple photolithography conditions.

Abstract: A cap nitride stack which prevents etch penetration to the HDP nitride while maintaining the electromigration benefits of HDP nitride atop Cu. In one embodiment, the stack comprises a first layer of HDP nitride and a second layer of a Si—C—H compound disposed over the first layer. The Si—C—H compound is for example BLoK, or N-BLoK (Si—C—H—N), and is selected from a group of materials that has high selectivity during via RIE such that RIE chemistry from the next wiring level does not punch through. Carbon and nitrogen are the key elements. In another embodiment, the stack comprises a first layer of HDP nitride, followed by a second layer of UVN (a plasma nitride), and a third layer comprising HDP nitride disposed over the second layer.

Abstract: A cap nitride stack which prevents etch penetration to the HDP nitride while maintaining the electromigration benefits of HDP nitride atop Cu. In one embodiment, the stack comprises a first layer of HDP nitride and a second layer of a Si—C—H compound disposed over the first layer. The Si—C—H compound is for example BLoK, or N-BLoK (Si—C—H—N), and is selected from a group of materials that has high selectivity during via RIE such that RIE chemistry from the next wiring level does not punch through. Carbon and nitrogen are the key elements. In another embodiment, the stack comprises a first layer of HDP nitride, followed by a second layer of UVN (a plasma nitride), and a third layer comprising HDP nitride disposed over the second layer.

Abstract: A method for forming a semiconductor wafer comprising of applying a first patterned resist to at least one first predetermined region of a wafer where said at least one first predetermined region of said wafer are protected by said first patterned resist and a first remaining portion of said wafer is not protected by said first patterned resist; etching said first remaining portion of said wafer not protected by said first pattern resist; stripping the first pattern resist from said wafer; applying a second patterned resist to at least one second pre-determined region of said wafer where said at least one second predetermined region of said wafer are protected by a second patterned resist and a second remaining portion is not protected by said second patterned resist; etching said second remaining portion not protected by said second patterned resist; and stripping said second patterned resist from said wafer.

Abstract: The present invention provides photolithographic device and method for optimizing the photolithography process window. The photolithography device comprises a substrate; and a pattern layer having radiant energy transparent portions and radiant energy blocking portions, where the pattern layer has features with a varying overlay. The overlay tolerance is determined by varying the misalignment the features of the pattern. The photolithography device is a reticle. The method for determining an optimum photolithography process window comprises exposing a portion of a wafer to a pattern produced by a reticle, the pattern having a varying overlay that produces multiple photolithography conditions, wherein each photolithography condition has an overlay tolerance; and stepping the reticle across a remaining portion of the wafer, where each step exposes an other region of the wafer to the pattern producing multiple photolithography conditions.

Abstract: A predictive method is used to compensate for intermediate batch sensitivities which inevitably occur during resist batch changeover. The compensation is applied to historical dose levels to arrive at a new dose level estimating an optimum dose. When the system discovers that a new batch of resist is loaded to a tool, historical data is used to calculate a reference dose for each tool. A batch factor is continuously calculated and using historical data along with the batch factor, a dose adjustment is made to maintain proper image size.

Abstract: A method for forming a semiconductor wafer comprising of applying a first patterned resist to at least one first predetermined region of a wafer where said at least one first predetermined region of said wafer are protected by said first patterned resist and a first remaining portion of said wafer is not protected by said first patterned resist; etching said first remaining portion of said wafer not protected by said first pattern resist; stripping the first pattern resist from said wafer; applying a second patterned resist to at least one second predetermined region of said wafer where said at least one second predetermined region of said wafer are protected by a second patterned resist and a second remaining portion is not protected by said second patterned resist; etching said second remaining portion not protected by said second patterned resist; and stripping said second patterned resist from said wafer.

Abstract: A mask/wafer control structure and an algorithm for placement thereof provide for data placement of measurement control structures, called a PLS, Process limiting Structure, on a mask and a plurality of chips on the wafer which provide for tighter control of both mask manufacture and wafer production by providing the most critical design structures for measurement during creation of the mask, and in the photolithography and etch processes. The PLS structures are located at multiple locations throughout the chip, and so they receive the same data preparation as the chip, and measurement tools are able to measure the same features at each fabrication step from fabrication of the mask to final formation of the etched features. Manufacturing control and the interlock between the wafer fabrication and the mask fabrication are enhanced, allowing for improved quality of the final product.

Abstract: A predictive method is used to compensate for intermediate batch sensitivities which inevitably occur during resist batch changeover. The compensation is applied to historical dose levels to arrive at a new dose level estimating an optimum dose. When the system discovers that a new batch of resist is loaded to a tool, historical data is used to calculate a reference dose for each tool. A batch factor is continuously calculated and using historical data along with the batch factor, a dose adjustment is made to maintain proper image size.

Abstract: A method and system for determining overlay tolerances. The method comprises the steps of exposing wafers at different critical dimensions (preferably, above, below, and at optimum image size); and varying the overlay across each wafer, preferably by intentionally increasing the magnification. Functional yield data are used to determine the overlay tolerance for each of the image sizes. The present invention, thus, studies the interaction of image size and feature misalignment. Prior to this invention, the only way to attain this information was to process a large number of lots and create a trend of image size and alignment vs. yield. The present invention solves the problem by determining the overlay tolerance based on yield data from a single lot. The design can then be altered or the overlay limit can be tightened (or relaxed) based on failure analysis of the regions/features that are most sensitive to misalignment.

Abstract: A predictive method is used to compensate for intermediate batch sensitivities which inevitably occur during resist batch changeover. The compensation is applied to historical dose levels to arrive at a new dose level estimating an optimum dose. When the system discovers that a new batch of resist is loaded to a tool, historical data is used to calculate a reference dose for each tool. A batch factor is continuously calculated and using historical data along with the batch factor, a dose adjustment is made to maintain proper image size.

Abstract: A mask/wafer control structure and an algorithm for placement thereof provide for data placement of measurement control structures, called a PLS, Pitch and Linearity Structure, on a mask and a plurality of chips on the wafer which provide for tighter control of both mask manufacture and wafer production by providing the most critical design structures for measurement during creation of the mask, and in the photolithography and etch processes. The PLS structures are located at multiple locations throughout the chip, so they receive the same data preparation as the chip, and measurement tools are able to measure the same features at each fabrication step from fabrication of the mask to final formation of the etched features.

Abstract: A predictive method is used to compensate for intermediate batch sensitivities which inevitably occur during resist batch changeover. The compensation is applied to historical dose levels to arrive at a new dose level estimating an optimum dose. When the system discovers that a new batch of resist is loaded to a tool, historical data is used to calculate a reference dose for each tool. A batch factor is continuously calculated and using historical data along with the batch factor, a dose adjustment is made to maintain proper image size.

Abstract: A method and system for determining overlay tolerances. The method comprises the steps of exposing wafers at different critical dimensions (preferably, above, below, and at optimum image size); and varying the overlay across each wafer, preferably by intentionally increasing the magnification. Functional yield data are used to determine the overlay tolerance for each of the image sizes. The present invention, thus, studies the interaction of image size and feature misalignment. Prior to this invention, the only way to attain this information was to process a large number of lots and create a trend of image size and alignment vs. yield. The present invention solves the problem by determining the overlay tolerance based on yield data from a single lot. The design can then be altered or the overlay limit can be tightened (or relaxed) based on failure analysis of the regions/features that are most sensitive to misalignment.