Abstract: A glitchless terminal count indication digital counter having a clock signal as an input thereto is disclosed and comprises a state logic means comprised of a plurality of DQ flip-flops for providing a digital count with the clock signal being sent to an input thereof, a next state decode means, a next terminal count decode means for providing an indication at its output that the digital output count will reach a terminal count at the next clock cycle, and a terminal count logic means for obtaining the indication from the next terminal count decode means and providing therefrom at the next clock cycle a glitchless terminal count indication. The next state decode means has inputs and outputs, with the digital count being an input thereto, and the state logic means and the next terminal count decode means being coupled to the output thereof.