Patents by Inventor Matthew Call

Matthew Call has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9875025
    Abstract: Systems and methods for retaining data are disclosed in which refresh copy operations are performed on data stored in non-volatile solid-state memory. A controller may be configured to maintain a list of physical memory locations, the list sorted by a least recently used criterion. The controller may select a first entry from a top of the list and perform a refresh operation to copy data stored in a current physical memory location associated with the first entry to a new physical memory location, and may remove the first entry from the top of the list and add a new entry associated with the new physical memory location to a bottom of the list. The controller may repeat the select, perform, remove and add steps for a plurality of entries in the list, and the steps may be timed such that all refresh operations are performed for all of the plurality of entries within a set period of time.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: January 23, 2018
    Assignee: Western Digital Technologies, Inc
    Inventors: Mei-Man L. Syu, Matthew Call, Ho-Fan Kang, Lan D. Phan
  • Patent number: 9652379
    Abstract: Embodiments of the invention are directed to enabling concurrent commands from command requesters in a non-volatile solid-state storage subsystem in a manner that reduces contentions among the commands. Embodiments group blocks of memory into multiple sets of superblocks and associate a command requester to each superblock set. In one embodiment, the superblock sets are dynamically associated with a requester. In one embodiment, the superblock sets are dynamically associated with requesters based in part on at least one of internal memory management needs and host command throughput. In one embodiment, an erase command is executed on a superblock within a set and a simultaneous write command is executed on a superblock within another set.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: May 16, 2017
    Assignee: Western Digital Technologies, Inc.
    Inventors: Mei-Man L. Syu, Matthew Call, Ho-Fan Kang, Lan D. Phan
  • Publication number: 20160004446
    Abstract: Systems and methods for retaining data in non-volatile solid-state memory are disclosed in which refresh copy operations are performed on data stored in non-volatile solid-state memory. A controller may be configured to issue copy commands and to maintain usage data on a storage subsystem. A refresh copy operation helps ensure that data written to memory retain integrity by causing data to be programmed again onto the memory, which minimizes the risk of data error caused by electron leak in the non-volatile solid-state memory. The controller may be configured to maintain a list of physical memory locations storing data in non-volatile solid-state memory array, where the list is sorted by a least recently used criterion. In one embodiment, the controller may select a first entry from a top of the list for processing and issue a copy command stored in a current physical memory location associated with the first entry to a new physical memory location.
    Type: Application
    Filed: September 14, 2015
    Publication date: January 7, 2016
    Inventors: Mei-Man L. SYU, Matthew CALL, Ho-Fan KANG, Lan D. PHAN
  • Patent number: 9135166
    Abstract: Systems and methods for retaining data in non-volatile solid-state memory are disclosed in which refresh copy operations are performed on data stored in non-volatile solid-state memory. A controller can comprise a data retention module configured to issue copy commands within different periods of time and to maintain usage data on a storage subsystem. A refresh copy operation helps ensure that data written to memory retain integrity by causing data to be programmed again onto the memory. Execution of refresh copy commands may be prioritized over other commands based on a remaining length of time. One or more data structures may be used to determine memory blocks that require refresh copy operations. In one embodiment, a validity bit array is used to track blocks that contain valid data. In another embodiment, a least recently used list is used to track blocks that have been least recently written.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: September 15, 2015
    Assignee: Western Digital Technologies, Inc.
    Inventors: Mei-Man L. Syu, Matthew Call, Ho-Fan Kang, Lan D. Phan
  • Patent number: 9110835
    Abstract: In one embodiment of the invention, a flash-based/solid-state storage system with an implemented data redundancy scheme such as RAID is configured to hold parity data in a volatile memory such as RAM and write such parity data to the non-volatile flash media when a full stripe of data has been written to the media. Other embodiments in certain situations force an early write of the parity for a partial stripe that has not been fully written to the non-volatile media. Those situations may include a data access error on data in a partial stripe and a detected power loss event with a partial stripe present. Embodiments are directed to writing additional data with the parity data for the partial stripe and then later using the additional data in data recovery. This approach allows the controller to easily detect the presence of a partial stripe and handle such a stripe accordingly.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: August 18, 2015
    Assignee: Western Digital Technologies, Inc.
    Inventors: Matthew Call, John A. Morrison, Lan D. Phan, Mei-Man L. Syu
  • Patent number: 9042197
    Abstract: Systems and methods for early warnings of power loss in solid state storage drives are disclosed. Early warnings of power loss can be used to power the drive to force the drive into a low power states before the energy in backup power sources, such as backup capacitors, is used. The low power states can allow for the reduction of power use by the drive which can provide cost savings and reduction in the risk that the drive will be rendered reconfigurable by a power failure event.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: May 26, 2015
    Assignee: Western Digital Technologies, Inc.
    Inventors: Michael S. Allison, Stephen J. Silva, Johnny A. Lam, Matthew Call
  • Publication number: 20150029808
    Abstract: Systems and methods for early warnings of power loss in solid state storage drives are disclosed. Early warnings of power loss can be used to power the drive to force the drive into a low power states before the energy in backup power sources, such as backup capacitors, is used. The low power states can allow for the reduction of power use by the drive which can provide cost savings and reduction in the risk that the drive will be rendered reconfigurable by a power failure event.
    Type: Application
    Filed: September 6, 2013
    Publication date: January 29, 2015
    Applicant: Western Digital Technologies, Inc.
    Inventors: MICHAEL S. ALLISON, STEPHEN J. SILVA, JOHNNY A. LAM, MATTHEW CALL
  • Patent number: 8924629
    Abstract: A non-volatile storage system is disclosed which provides a mapping table which includes a granularity which does not correspond to the page size of a non-volatile storage array. A reduced mapping table granularity enables more than one mapping entry to exist in a single page on the solid-state array. A write command which does not exceed a mapping table entry can invalidate only a portion of the written page, and can be combined with a second write command to write a new page of the solid-state array.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: December 30, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventors: Matthew Call, Robert L. Horn, Mei-Man L. Syu, Lan D. Phan, John A. Morrison, Ho-Fan Kang
  • Patent number: 8793429
    Abstract: A non-volatile storage system is provided with reduced delays associated with loading and updating a logical-to-physical mapping table from non-volatile memory. The mapping table is stored in a plurality of segments, so that each segment can be loaded individually. The segmented mapping table allows memory access to logical addresses associated with the loaded segment when the segment is loaded, rather than delaying accesses until the entire mapping table is loaded. When loading mapping segments, segments can be loaded according to whether there is a pending command or by an order according to various algorithms.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: July 29, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventors: Matthew Call, Lyndon S. Chiu, Robert L. Horn, Lan D. Phan
  • Patent number: 8769190
    Abstract: Embodiments of the invention are directed to enabling concurrent commands from command requesters in a non-volatile solid-state storage subsystem in a manner that reduces contentions among the commands. Embodiments group blocks of memory into multiple sets of superblocks and associate a command requester to each superblock set. In one embodiment, the superblock sets are dynamically associated with a requester. In one embodiment, the superblock sets are dynamically associated with requesters based in part on at least one of internal memory management needs and host command throughput. In one embodiment, an erase command is executed on a superblock within a set and a simultaneous write command is executed on a superblock within another set.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: July 1, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventors: Mei-Man L. Syu, Matthew Call, Ho-Fan Kang, Lan D. Phan
  • Patent number: 8700951
    Abstract: In one embodiment of the invention, a flash-based/solid-state storage system with an implemented data redundancy scheme such as RAID is configured to hold parity data in a volatile memory such as RAM and write such parity data to the non-volatile flash media when a full stripe of data has been written to the media. Other embodiments in certain situations force an early write of the parity for a partial stripe that has not been fully written to the non-volatile media. Those situations may include a data access error on data in a partial stripe and a detected power loss event with a partial stripe present. Embodiments are directed to writing additional data with the parity data for the partial stripe and then later using the additional data in data recovery. This approach allows the controller to easily detect the presence of a partial stripe and handle such a stripe accordingly.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: April 15, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventors: Matthew Call, John A. Morrison, Lan D. Phan, Mei-Man L. Syu
  • Patent number: 8612669
    Abstract: Systems and methods for retaining data in non-volatile solid-state are disclosed in which refresh copy operations are performed on data stored in non-volatile solid-state memory. A controller can comprise a data retention module configured to issue copy commands within different periods of time, and to maintain usage data on a storage subsystem. A refresh copy operation helps ensure that data written to memory retain integrity by causing data to be programmed again onto the memory, which minimizes the risk of data error caused by electron leak in the non-volatile solid-state memory. One or more data structures may be used to determine memory blocks that require refresh copy operations. In one embodiment, a validity bit array is used to track blocks that contain valid data. In another embodiment, a least recently used list is used to track blocks that have been least recently written.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: December 17, 2013
    Assignee: Western Digital Technologies, Inc.
    Inventors: Mei-Man L. Syu, Matthew Call, Ho-Fan Kang, Lan D. Phan
  • Patent number: 8423722
    Abstract: Solid State Drives (SSD) can yield very high performance if it is designed properly. A SSD typically includes both a front end that interfaces with the host and a back end that interfaces with the flash media. Typically SSDs include flash media that is designed with a high degree of parallelism that can support a very high bandwidth on input/output (I/O). A SSD front end designed according to a traditional hard disk drive (HDD) model will not be able to take advantage of the high performance offered by the typical flash media. Embodiments of the invention provide improved management of multiple I/O threads that take advantage of the high performing and concurrent nature of the back end media, so the resulting storage system can achieve a very high performance.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: April 16, 2013
    Assignee: Western Digital Technologies, Inc.
    Inventors: Marvin R. Deforest, Matthew Call, Mei-Man L. Syu