Abstract: In a data processing system that includes redundant elements, a method for protecting system components from transients that arise on a system interconnect during switching events. The system components operate in a normal mode of operation prior to detection of the impending occurrence of a switching event wherein a first redundant element replaces a failed element. Upon detecting the impending occurrence of a switching event, an indication that the switching event is to occur is conveyed to the system components. The system components respond by entering a standby mode of operation wherein system components isolate their circuitry from the system interconnect during the switching event. The system components returning to the normal mode of operation in response to a triggering event.

Abstract: In a data processing system that includes a plurality of system components coupled to a time division multiplexed data bus, a computer-implemented method for assigning a plurality of transmission opportunities within a transmission cycle among the plurality of system components. A system component is selected, and the number of transmission opportunities within the transmission cycle required by the system component is determined. Transmission opportunities are assigned to the system component such that each transmission opportunity is evenly spaced from a next transmission opportunity within an acceptable margin of error. The process is repeated for each system component.

Abstract: A data processing system. The data processing system includes a time division multiplexed (TDM) bus and a plurality of system components coupled to the TDM data bus. A memory stores a table of allocation entries. Each allocation entry indicates which one of the plurality of system components, if any, to be allocated a corresponding bandwidth unit (BU), wherein each BU comprises a contiguous block of TDM timeslots. An allocation control circuit is coupled to the system components and the memory for accessing the allocation table and allocating BUs to the system components on a BU-by-BU basis so that the allocation control circuit operates at a slower speed than the TDM data bus.

Abstract: A data processing system. The data processing comprises a data bus subdivided into a plurality of independent data paths and a plurality of system components coupled to the data bus. Each system component monitors each independent data path of the data bus to determine whether that system components is to receive data transmitted via that independent data path. An allocation control circuit coupled to the system components allocates a transmission opportunity spanning multiple bus clock cycles to a first system component such that the first system component is enabled to transmit data via any and all of the independent data paths during the transmission opportunity. The allocation control circuit enables the first system component to begin transmission of data over the data paths at different clock cycles of the transmission opportunity such that the plurality of system components need monitor only one independent data path per bus clock cycle.