Abstract: An apparatus, including: a switched capacitor configured to generate a switched capacitor voltage based on an input clock signal and a current; a current digital-to-analog converter (DAC) configured to generate the current based on a first digital signal; a first reference voltage generator configured to generate a first reference voltage; and a first voltage comparing device configured to generate a first frequency deviation detection signal based on a comparison of the switched capacitor voltage to the first reference voltage.

Abstract: An apparatus, including: a switched capacitor configured to generate a switched capacitor voltage based on an input clock signal and a current; a current digital-to-analog converter (DAC) configured to generate the current based on a first digital signal; a first reference voltage generator configured to generate a first reference voltage; and a first voltage comparing device configured to generate a first frequency deviation detection signal based on a comparison of the switched capacitor voltage to the first reference voltage.

Abstract: An IC includes a first set of MOS transistors configured to have a common first transistor source/drain terminal A, a first transistor gate, and a first transistor source/drain terminal B. In addition, the IC includes a first plurality of interconnect stacks coupled to the first transistor source/drain terminal A. Each interconnect stack of the first plurality of interconnect stacks extends in a second direction over at least a portion of the first set of MOS transistors and includes consecutive metal layer interconnects. Further, the IC includes a first comb interconnect structure extending in a first direction orthogonal to the second direction, with comb fingers extending in the second direction over at least a portion of the first set of MOS transistors and the first plurality of interconnect stacks. The first comb interconnect structure is coupled to the first plurality of interconnect stacks.

Abstract: An IC includes a first set of MOS transistors configured to have a common first transistor source/drain terminal A, a first transistor gate, and a first transistor source/drain terminal B. In addition, the IC includes a first plurality of interconnect stacks coupled to the first transistor source/drain terminal A. Each interconnect stack of the first plurality of interconnect stacks extends in a second direction over at least a portion of the first set of MOS transistors and includes consecutive metal layer interconnects. Further, the IC includes a first comb interconnect structure extending in a first direction orthogonal to the second direction, with comb fingers extending in the second direction over at least a portion of the first set of MOS transistors and the first plurality of interconnect stacks. The first comb interconnect structure is coupled to the first plurality of interconnect stacks.