Abstract: An electronic device can include a semiconductor layer having a primary surface, and an isolation structure. The isolation structure can include a first well region within the semiconductor layer and having a first conductivity, a second well region within the semiconductor layer and having a second conductivity type opposite the first conductivity type, and a third well region within the semiconductor layer having the first conductivity type. The second well region can be disposed between the first and third well regions. The first, second, and third well regions can be electrically connected to one another. The electronic device can help to allow more electrons during an electrostatic discharge or similar event to flow where the electrons will be less problematic. A process of forming the electronic device may be implemented with changes to existing masks without adding any processing operations.

Abstract: An electronic device can include a semiconductor layer having a primary surface, and an isolation structure. The isolation structure can include a first well region within the semiconductor layer and having a first conductivity, a second well region within the semiconductor layer and having a second conductivity type opposite the first conductivity type, and a third well region within the semiconductor layer having the first conductivity type. The second well region can be disposed between the first and third well regions. The first, second, and third well regions can be electrically connected to one another. The electronic device can help to allow more electrons during an electrostatic discharge or similar event to flow where the electrons will be less problematic. A process of forming the electronic device may be implemented with changes to existing masks without adding any processing operations.

Abstract: A method for making a heterojunction bipolar transistor on an insulated semiconductor substrate. A highly doped subcollector is formed on an insulated substrate. A lightly doped collector is formed adjacent to and in direct contact with the subcollector. An extrinsic base film stack is deposited on the lightly doped collector. A collector base S and base emitter junction window are etched in the extrinsic base film stack. A doped semiconductor intrinsic base is formed in the junction window. A self aligning base emitter spacer is formed and etched in the junction window and the emitter material is deposited and etched in the junction window. Oxide spacers are deposited and etched adjacent walls of the emitter material. The extrinsic base is defined and conductors are deposited on the device to provide a heterojunction bipolar transistor having improved resistance and capacitance characteristics.