Abstract: Aspects herein are directed to an apparel item that promotes thermo-regulation through the use of engineered openings, venting, and/or stand-off structures. In exemplary aspects, 20-45% of the apparel item may comprise the engineered openings. Vents may be positioned on the apparel item in areas that experience high amounts of air flow to help channel air into the apparel item. The stand-off structures may be positioned on an inner-facing surface of the apparel item where they help to create a space between the apparel item and the wearer's body surface in which air can flow and help cool the wearer by promoting evaporative cooling.

Abstract: A thread rolling die includes a thread rolling region comprising a working surface including a thread form. The thread rolling region of the thread rolling die comprises a sintered cemented carbide material having a hardness in the range of 78 HRA to 89 HRA. In certain embodiments, the thread rolling die may further include at least one non-cemented carbide piece metallurgically bonded to the thread rolling region in an area of the thread rolling region that does not prevent a workpiece from contacting the working surface, and wherein the non-cemented carbide piece comprises at least one of a metallic region and a metal matrix composite region. Methods of forming a thread rolling die as embodied herein are also disclosed.

Abstract: A multi-band electronically scanned array antenna including a first sub-assembly having electronic circuits for a first frequency band; a second sub-assembly mechanically coupled to the first sub-assembly and having electronic circuits for a second frequency band; and an aperture adjacent to the first sub-assembly, the aperture being shared by the first sub-assembly and the second sub-assembly. The array antenna may further include a band switching circuit, or a combining circuit for coupling the first sub-assembly or the second sub-assembly to the aperture. The array antenna may also include a third sub-assembly including electronic circuits for a third frequency band. In this way, the aperture is shared by the first sub-assembly, the second sub-assembly, and the third sub-assembly to provide a smaller and lighter array antenna.

Abstract: A multi-band electronically scanned array antenna including a first sub-assembly having electronic circuits for a first frequency band; a second sub-assembly mechanically coupled to the first sub-assembly and having electronic circuits for a second frequency band; and an aperture adjacent to the first sub-assembly, the aperture being shared by the first sub-assembly and the second sub-assembly. The array antenna may further include a band switching circuit, or a combining circuit for coupling the first sub-assembly or the second sub-assembly to the aperture. The array antenna may also include a third sub-assembly including electronic circuits for a third frequency band. In this way, the aperture is shared by the first sub-assembly, the second sub-assembly, and the third sub-assembly to provide a smaller and lighter array antenna.

Abstract: A thread rolling die includes a thread rolling region comprising a working surface including a thread form. The thread rolling region of the thread rolling die comprises a sintered cemented carbide material having a hardness in the range of 78 HRA to 89 HRA. In certain embodiments, the thread rolling die may further include at least one non-cemented carbide piece metallurgically bonded to the thread rolling region in an area of the thread rolling region that does not prevent a workpiece from contacting the working surface, and wherein the non-cemented carbide piece comprises at least one of a metallic region and a metal matrix composite region. Methods of forming a thread rolling die as embodied herein are also disclosed.

Abstract: According to an embodiment of the present invention, a subassembly for a phased array radar includes a substrate generally lying in a first plane, the substrate including a plurality of transmit/receive modules coupled to a mounting surface and a plurality of radiating elements formed adjacent the mounting surface, and a multi-function board generally lying in a second plane parallel to the first plane. The multi-function board is in spaced apart relation to the substrate and may include RF manifolding and logic/power distribution functions for the transmit/receive modules.

Abstract: According to an embodiment of the present invention, a multi-function carrier structure for a phased array radar includes a substrate that includes a mounting surface for a plurality of transmit/receive modules, a plurality of radiating elements integrally formed in the substrate adjacent the mounting surface, and a plurality of cooling channels integrally formed within a thickness of the substrate. The substrate is formed from a material having a coefficient of thermal expansion similar to respective substrates of the transmit/receive modules.

Abstract: According to an embodiment of the present invention, a transmit/receive module for a phased array radar includes a substrate, a ground plane formed outwardly from the substrate, and one or more dielectric layers formed outwardly from the ground plane. The one or more dielectric layers have RF and DC routing formed therein. The transmit/receive module further includes an electronic device coupled outwardly from the one or more dielectric layers, and a lid coupled to a portion of the one or more dielectric layers.

Abstract: A client signal received at an ingress interface is adapted to a higher-rate transport signal. Clock frequency acceleration is achieved by an M/N-multiplying PLL where the magnitude of M and N can be restricted without causing the rate of the resulting transport signal rate to deviate unacceptably from a nominal transport signal rate. Each frame of the transport signal has a payload section with a fixed number of transport payload bytes, each of which is either a dummy byte or a client byte. The number of client bytes per transport frame is within one byte of the number of client bytes actually received at the ingress interface during the duration of the frame. The designation of each frame as a low-fill frame or a high-fill frame is automatically regulated by checking the fill level of a memory element and is redundantly encoded by the ingress interface and transmitted to an egress interface as part of the frame.

Abstract: The present invention involves the passing of clock information from a point where a tributary payload is mapped into a carrier to a point where a tributary payload is de-mapped from the carrier. A synchronization signal is generated at the mapping end. Rather than sending clock phase information implicitly by means of the data, as is normally the case, a value of the synchronization signal at a given time, is sent explicitly, independent from the payload data.

Abstract: A system for recovering a clock signal from a data signal is described. The system uses an oscillator adapted to generate an oscillator output signal, a first detecting circuit for obtaining a coarse frequency-lock condition between the data signal and a recovered clock signal, a second detecting circuit for obtaining a phase-locked condition between the data signal and the recovered clock signal, a lock-detecting circuit responsive to the first detecting circuit for detecting an out-of-lock condition between the data signal and the recovered clock signal, and a control circuit responsive to the lock-detecting circuits and adapted to control the oscillator to generate an oscillator output signal on the basis of the first detecting circuit during an out-of-lock condition, and otherwise to generate the oscillator output signal on the basis of the second detecting circuit.

Abstract: A connection integrity monitor is provided wherein, for large switch fabrics (connection circuits), gate usage and power requirements are reduced by a value approaching 50% when compared to a previously disclosed connection integrity monitor. Rather than simultaneously monitoring the connectivity of all outputs of the switch fabric, thus completely duplicating the switch fabric, the connection integrity monitor monitors only one connection at a time. Therefore, redundancy is reduced from M to 1. The connection integrity monitor can be provisioned statically to monitor any one of the output connections or arranged so that all connections can be monitored, although not simultaneously.

Abstract: An apparatus and method is disclosed for attaching a data sub-channel to a digital payload data stream having a clock signal for communicating supplemental data within an optical communications network. At an upstream site the clock signal is phase-modulated with an encoded supplemental data stream to generate a phase-modulated sub-channel. The phase-modulated clock is used to time the payload data stream so as to superimpose the phase-modulated sub-channel onto the payload data stream. At a downstream site the sub-channel is recovered and the clock signal is used to retime the payload data stream. The sub-channel is then demodulated and the supplemental data stream decoded.

Abstract: The present invention relates to an optical communications system performance monitoring technique which provides for detecting bit disparity within a data stream. The average power value for a data stream is ascertained by passing the data stream through a low pass filter. The data stream's average power value is then compared with a bit stream baseline power value for a one bit stream and a zero bit stream, the resulting deviation comprising a bit disparity value. An embodiment of this invention would incorporate the use of threshold alarms set for unacceptably high levels of bit disparity. The triggering of these threshold alarms could initiate the transmission of automated customer warnings such as a notification that performance cannot be guaranteed due to high bit disparity on the signal.

Abstract: A bit disparity monitor is disclosed in which a data stream is sub-sampled and logical 1's are detected in the sub-sampled stream. Within a predetermined period, the number of logical 1's is counted and the ratio of logical 1's to the number of bits is determined and compared to acceptable thresholds of bit disparity. In a second embodiment, the data stream is inverted and both the original data stream and the inverted data stream are sampled. The number of logical 1's detected in the sub-sampled original data stream and the number of logical 0's in the sub-sampled inverted data stream are correlated and mismatches, indicative of a transitional sample, are discarded before the bit disparity ratio is determined. Methods of comparing the bit disparity of a data stream to an acceptable threshold are also disclosed.

Abstract: A method and apparatus for filtering phase noise or jitter from a reference signal that may be of any arbitrary rate. By using a synthesizer to convert a signal at the output of a low noise signal source to a signal with frequency similar to a high speed output rate with desired relationship to the reference signal, a limitation normally caused by the narrow tuning range of a VCXO (a typical low noise signal source) can be overcome. Conversely, the desired high speed output rate may be converted to one similar to the VCXO frequency.

Abstract: A direct digital frequency synthesizer includes inputs for a reference clock signal and a control word, and an output for a synthesized clock signal. A phase accumulator coupled to the input for the control word and the reference clock signal has an output for a phase control signal. A phase shifter has inputs for the reference clock signal and the phase control signal and an output coupled to the output for the synthesized clock signal. The control word can be used to adjust the output frequency and phase of the synthesized clock signal.