Patents by Inventor Matthew D. Jenkinson

Matthew D. Jenkinson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250217232
    Abstract: A memory module includes a number of memory devices. During a read operation the memory device reads data and parity bits. An error correction circuit of the memory device determines if there is an uncorrectable error in the data and parity bits. If there is an uncorrectable error, the error correction circuit aliases a bit within a specified subset of the data bits. The specified subset may be based on which patterns of errors are correctable by a module level error correction scheme.
    Type: Application
    Filed: December 6, 2024
    Publication date: July 3, 2025
    Applicant: Micron Technology, Inc.
    Inventors: Wesley W. Borie, Garth N. Grubb, Dennis G. Montierth, Matthew D. Jenkinson, Sujeet Ayyapureddi, Michael Schena
  • Publication number: 20250061017
    Abstract: Apparatuses, systems, and methods for correcting latch upset events in a trim register are described. An example method includes sending a command, from a controller, to access at least one block of a plurality of blocks of a non-volatile memory. The method can further include receiving a failure message associated with reading the at least one block. The method can further include, in response to receiving the failure message, resetting trim data associated with the plurality of blocks.
    Type: Application
    Filed: July 23, 2024
    Publication date: February 20, 2025
    Inventors: John M. Gonzales, Christopher G. Wieduwilt, Seth A. Eichmeyer, Matthew D. Jenkinson
  • Publication number: 20250061058
    Abstract: Apparatuses, systems, and methods for block status parity data are described. An example method includes storing block status data associated with at least one block of a non-volatile memory that indicates a status of the at least one block of memory within a controller. The example method further comprises storing parity data that corresponds to the block status data. The example method further comprises prior to writing the block status data to the non-volatile memory, comparing the stored block status data to the parity data.
    Type: Application
    Filed: July 19, 2024
    Publication date: February 20, 2025
    Inventors: John M. Gonzales, Christopher G. Wieduwilt, Seth A. Eichmeyer, Matthew D. Jenkinson
  • Publication number: 20250061016
    Abstract: Apparatuses, systems, and methods for block status data reset are described. An example method includes sending a command, from a controller, to access at least one block of a first memory device. The example method further comprises receiving a failure message from the first memory device due to the at least one block being tagged as a bad block in block status data of the first memory device. The example method further comprises in response to receiving the failure message, resetting the block status data by reloading previously stored block status data from a second memory device.
    Type: Application
    Filed: July 25, 2024
    Publication date: February 20, 2025
    Inventors: John M. Gonzales, Christopher G. Wieduwilt, Seth A. Eichmeyer, Matthew D. Jenkinson
  • Publication number: 20250061020
    Abstract: Apparatuses, systems, and methods for tracking latch upset events using a trim register are described. An example method includes reading trim data from trim registers in a non-volatile memory device. The example method can further include generating parity data for the trim data. The example method can further include storing the parity data in the trim registers. The example method can further include, subsequent to the generation and storage of the parity data, re-reading the trim data from the trim registers, generating additional parity data, and comparing the parity data to the additional parity data.
    Type: Application
    Filed: July 19, 2024
    Publication date: February 20, 2025
    Inventors: John M. Gonzales, Christopher G. Wieduwilt, Seth A. Eichmeyer, Matthew D. Jenkinson
  • Publication number: 20250060893
    Abstract: Apparatuses, systems, and methods for tracking latch upset events using block status data are described. An example method includes tracking a block status of each of a plurality of blocks of a first memory device by storing a first set of block status data that indicates a status of each block of the plurality of blocks in the first memory device and storing a second set of block status data that indicates a status of each block of the plurality of blocks in a location. The example method further includes comparing the first set of block status data to the second set of block status data.
    Type: Application
    Filed: July 23, 2024
    Publication date: February 20, 2025
    Inventors: John M. Gonzales, Christopher G. Wieduwilt, Seth A. Eichmeyer, Matthew D. Jenkinson
  • Patent number: 12223099
    Abstract: A memory device includes a plurality of fuse banks for a memory region. Each fuse bank stores bit information that relates to at least one of a default address for the plurality of fuse banks or an address of a memory cell that is defective. A default address protection circuit is configured to provide a default address status signal indicating whether a fuse bank in the plurality of fuse banks is storing bit information that corresponds to both the default address and an address of a memory cell that is defective. The memory device include a no_match circuit that overrides a repair of the external memory address if the external address matches the default address and if the default address status signal indicates that no fuse bank is storing bit information that corresponds to both the default address and an address of a memory cell that is defective.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: February 11, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Seth A. Eichmeyer, Christopher G. Wieduwilt, Matthew D. Jenkinson
  • Patent number: 11948655
    Abstract: Methods, systems, and devices for indicating a blocked repair operation are described. A first indication of whether an address of a memory device is valid may be stored. After the first indication is stored, a command for accessing the address may be processed. Based on processing the command, a second indication of whether the address is valid may be obtained, and a determination of whether to perform or prevent a repair operation for repairing the address may be made based on the first indication and the second indication. A third indication of whether the repair operation was performed or prevented may be stored.
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: April 2, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Seth A. Eichmeyer, Christopher G. Wieduwilt, Matthew D. Jenkinson, Matthew A. Prather
  • Publication number: 20240062798
    Abstract: An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.
    Type: Application
    Filed: September 14, 2023
    Publication date: February 22, 2024
    Inventors: Timothy B. Cowles, Jiyun Li, Beau D. Barry, Matthew D. Jenkinson, Nathaniel J. Meier, Michael A. Shore, Adam J. Grenzebach, Dennis G. Montierth
  • Patent number: 11829243
    Abstract: Methods, systems, and devices for error evaluation for a memory system are described. A memory device may be configured to monitor access errors of the memory device to evaluate a likelihood that such errors are related to a failure of the memory device itself or to a failure outside the memory device. For example, a memory device may monitor a respective quantity of errors for each of a set of banks and, if the memory device detects that multiple banks are associated with a threshold quantity of access errors, the memory device may infer the presence of a failure outside the memory device. The memory device may store an indication of such a detection, which may be used to support failure diagnosis or resolution efforts, such as refraining from replacing a memory device when access errors are more likely to be the result of a system failure.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: November 28, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Matthew D. Jenkinson, Seth A. Eichmeyer, Christopher G. Wieduwilt
  • Publication number: 20230343409
    Abstract: Methods, systems, and devices for indicating a blocked repair operation are described. A first indication of whether an address of a memory device is valid may be stored. After the first indication is stored, a command for accessing the address may be processed. Based on processing the command, a second indication of whether the address is valid may be obtained, and a determination of whether to perform or prevent a repair operation for repairing the address may be made based on the first indication and the second indication. A third indication of whether the repair operation was performed or prevented may be stored.
    Type: Application
    Filed: April 21, 2022
    Publication date: October 26, 2023
    Inventors: Seth A. Eichmeyer, Christopher G. Wieduwilt, Matthew D. Jenkinson, Matthew A. Prather
  • Patent number: 11798610
    Abstract: An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: October 24, 2023
    Inventors: Timothy B. Cowles, Jiyun Li, Beau D. Barry, Matthew D. Jenkinson, Nathaniel J. Meier, Michael A. Shore, Adam J. Grenzebach, Dennis G. Montierth
  • Publication number: 20230315918
    Abstract: A memory device includes a plurality of fuse banks for a memory region. Each fuse bank stores bit information that relates to at least one of a default address for the plurality of fuse banks or an address of a memory cell that is defective. A default address protection circuit is configured to provide a default address status signal indicating whether a fuse bank in the plurality of fuse banks is storing bit information that corresponds to both the default address and an address of a memory cell that is defective. The memory device include a no_match circuit that overrides a repair of the external memory address if the external address matches the default address and if the default address status signal indicates that no fuse bank is storing bit information that corresponds to both the default address and an address of a memory cell that is defective.
    Type: Application
    Filed: March 28, 2022
    Publication date: October 5, 2023
    Inventors: Seth A. Eichmeyer, Christopher G. Wieduwilt, Matthew D. Jenkinson
  • Publication number: 20230222032
    Abstract: Methods, systems, and devices for error evaluation for a memory system are described. A memory device may be configured to monitor access errors of the memory device to evaluate a likelihood that such errors are related to a failure of the memory device itself or to a failure outside the memory device. For example, a memory device may monitor a respective quantity of errors for each of a set of banks and, if the memory device detects that multiple banks are associated with a threshold quantity of access errors, the memory device may infer the presence of a failure outside the memory device. The memory device may store an indication of such a detection, which may be used to support failure diagnosis or resolution efforts, such as refraining from replacing a memory device when access errors are more likely to be the result of a system failure.
    Type: Application
    Filed: January 10, 2022
    Publication date: July 13, 2023
    Inventors: Matthew D. Jenkinson, Seth A. Eichmeyer, Christopher G. Wieduwilt
  • Patent number: 11417383
    Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for dynamic refresh allocation. Memories may be subject to row hammer attacks, where one or more wordlines are repeatedly accessed to cause data degradation in victim rows nearby to the hammered wordlines. A memory may perform background auto-refresh operations, and targeted refresh operations where victim wordlines are refreshed. The memory may monitor access patterns to the memory in order to dynamically allocate the number of targeted refresh operations and auto-refresh operations in a set of refresh operations based on if a hammer attack is occurring and the type of hammer attack which is occurring.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: August 16, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Matthew D. Jenkinson, Nathaniel J. Meier, Dennis G. Montierth
  • Patent number: 11302374
    Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for dynamic refresh allocation. Memories may be subject to row hammer attacks, where one or more wordlines are repeatedly accessed to cause data degradation in victim rows nearby to the hammered wordlines. A memory may perform background auto-refresh operations, and targeted refresh operations where victim wordlines are refreshed. The memory may monitor access patterns to the memory in order to dynamically allocate the number of targeted refresh operations and auto-refresh operations in a set of refresh operations based on if a hammer attack is occurring and the type of hammer attack which is occurring.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: April 12, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Matthew D. Jenkinson, Nathaniel J. Meier, Dennis G. Montierth
  • Patent number: 11200942
    Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for lossy row access counting. Row addresses along a to address bus may be sampled. When the row address is sampled it may be compared to a plurality of stored addresses in a data storage unit. If the sampled address matches one of the stored addresses, a count value associated with that address may be updated in a first direction (such as being increased). Periodically, all of the count values may also be updated in a second direction (for example, decreased).
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: December 14, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Matthew D. Jenkinson, Jiyun Li, Dennis G. Montierth, Nathaniel J. Meier
  • Publication number: 20210304813
    Abstract: An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.
    Type: Application
    Filed: June 15, 2021
    Publication date: September 30, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Timothy B. Cowles, Jiyun Li, Beau D. Barry, Matthew D. Jenkinson, Nathaniel J. Meier, Michael A. Shore, Adam J. Grenzebach, Dennis G. Montierth
  • Patent number: 11069393
    Abstract: An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: July 20, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Timothy B. Cowles, Jiyun Li, Beau D. Barry, Matthew D. Jenkinson, Nathaniel J. Meier, Michael A. Shore, Adam J. Grenzebach, Dennis G. Montierth
  • Publication number: 20210183433
    Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for dynamic refresh allocation. Memories may be subject to row hammer attacks, where one or more wordlines are repeatedly accessed to cause data degradation in victim rows nearby to the hammered wordlines. A memory may perform background auto-refresh operations, and targeted refresh operations where victim wordlines are refreshed. The memory may monitor access patterns to the memory in order to dynamically allocate the number of targeted refresh operations and auto-refresh operations in a set of refresh operations based on if a hammer attack is occurring and the type of hammer attack which is occurring.
    Type: Application
    Filed: February 26, 2021
    Publication date: June 17, 2021
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Matthew D. Jenkinson, Nathaniel J. Meier, Dennis G. Montierth