Abstract: A digital display includes a plurality of pixel rows. For each pixel row, the digital display includes an EM gate driver configured to supply the pixel row with a luminance-controlling signal during each of a plurality of image frames. A luminance controller is configured to instruct the EM gate drivers to supply a pulse-width modulated signal to the plurality of pixel rows. Some pixel rows are supplied with a pulse-width modulated signal starting with an on pulse, and some pixel rows are supplied with a pulse-width modulated signal starting with an off pulse, on the same or different image frames.

Abstract: Examples are disclosed herein that relate to displaying modification regions on a multi-display device. One example provides a multi-display device comprising a plurality of displays, the multi-display device storing line offset data defining a line offset to apply to a displayed image to correct for display misalignment, and modification region data defining one or more modification regions that each modifies an appearance of the displayed image. The multi-display device is configured to set a displayed location of a first active area based upon the line offset data for a first display, and set a displayed location of a first modification region for the first display based upon the line offset data for the first display.

Abstract: Examples are disclosed herein that relate to displaying modification regions on a multi-display device. One example provides a multi-display device comprising a plurality of displays, the multi-display device storing line offset data defining a line offset to apply to a displayed image to correct for display misalignment, and modification region data defining one or more modification regions that each modifies an appearance of the displayed image. The multi-display device is configured to set a displayed location of a first active area based upon the line offset data for a first display, and set a displayed location of a first modification region for the first display based upon the line offset data for the first display.

Abstract: A display device includes a first display panel including N input/output (I/O) pads [I/O1 to I/ON] at a first side of the display device. A first display driver is operatively connected to the N I/O pads of the first display panel at the first side of the display device. A second display panel includes the N I/O pads at the first side of the display device. I/O pads I/O1+M and I/ON?M are a same type of I/O pad for M=0 to M=P for the first display panel and the second display panel. A second display driver, having a same configuration as the first display driver is operatively connected to the N I/O pads of the second display panel at the first side of the display device. A hinge pivotably connects the first display panel to the second display panel.

Abstract: A display device includes a first display panel including N input/output (I/O) pads [I/O1 to I/ON] at a first side of the display device. A first display driver is operatively connected to the N I/O pads of the first display panel at the first side of the display device. A second display panel includes the N I/O pads at the first side of the display device. I/O pads I/O1+M and I/ON?M are a same type of I/O pad for M=0 to M=P for the first display panel and the second display panel. A second display driver, having a same configuration as the first display driver is operatively connected to the N I/O pads of the second display panel at the first side of the display device. A hinge pivotably connects the first display panel to the second display panel.

Abstract: A method that enables an adaptive low power display device is described herein. The method includes determining a blocked area of a panel display, wherein the panel display is to render one or more images and deriving a segmented area of the display based on the blocked area of the display. The method also includes adjusting a segment of a backlight of the panel display that is proximate to the blocked area of the panel display according to a sparse array configuration, wherein the backlight is non-uniform in emitting light.

Abstract: A code sequence relayed to an infrared blaster is monitored. If the code sequence approaches a violating sequence, the infrared blaster is controlled to emit infrared light with a corrected sequence that does not express the violating sequence. If the code sequence does not approach the violating sequence, the infrared blaster is controlled to emit infrared light with the code sequence.

Abstract: A code sequence relayed to an infrared blaster is monitored. If the code sequence approaches a violating sequence, the infrared blaster is controlled to emit infrared light with a corrected sequence that does not express the violating sequence. If the code sequence does not approach the violating sequence, the infrared blaster is controlled to emit infrared light with the code sequence.

Abstract: A technique for performing a time slot interchange in a processor. The TSI process is surrounded by a multiplexing/demultiplexing circuit for converting a plurality of PCM highways into a single input serial data stream. The mux/demux circuit includes elastic stores to align frames and shift resisters to mux/demux with a minimum of delay. The TSI processor includes an input and an output buffered series port, a pair of input buffers, one to receive even-numbered frames from the PCM highways and one to receive odd-numbered frames, and an output buffer. Data is read from the appropriate input buffer in a non-sequential fashion as commanded by the processor in accordance with information stored in connection arrays (address buffers). The data is then written to the output buffer sequentially. The timing of the reading and writing steps is optimized relative to free running buffered serial port pointers for each BSP to reduce the frame delay.

Abstract: A method, apparatus, and system for determining and indicating packet queue readiness.

Abstract: A multiplexer for multiplexing and demultiplexing signals between a low-speed network and a higher speed network includes 7 quad DSX-1 cards and 1 spare card. The spare card is connected to the DSX-1 cards to allow the spare card to automatically be switched in for one of the DSX-1 cards or to allow interface electronics on the spare card to replace selected ones of interface electronics on different DSX-1 cards simultaneously. A pair of controller cards, a primary card and a secondary card, perform M1-3 multiplexing and demultiplexing and the DS-3 framing and transceiving. The controller cards can be selected or deselected in a short time period alarms are not set off and so that the transition is hitless by electronically enabling and disabling the transceiver. The multiplexer is connectable to 2 different T-3 links to provide network redundancy. An array of relays connected either controller card to either of the T-3 links.

Abstract: A technique for performing a time slot interchange in a processor. The TSI process is surrounded by a multiplexing/demultiplexing circuit for converting a plurality of PCM highways into a single input serial data stream. The mux/demux circuit includes elastic stores to align frames and shift resisters to mux/demux with a minimum of delay. The TSI processor includes an input and an output buffered serial port, a pair of input buffers, one to receive even-numbered frames from the PCM highways and one to receive odd-numbered frames, and an output buffer. Data is read from the appropriate input buffer in a non-sequential fashion as commanded by the processor in accordance with information stored in connection arrays (address buffers). The data is then written to the output buffer sequentially. The timing of the reading and writing steps is optimized relative to free running buffered serial port pointers for each BSP to reduce the frame delay.

Abstract: A multiplexer device for multiplexing and demultiplexing signals between a low-speed network including 28 DSX-1 signals and a relatively higher speed network including a DS-3 signal. The multiplexer device includes 7 quad DSX-1 cards and 1 spare card. The spare card is connected to the other 7 DSX-1 cards in a fashion that allows the spare card to automatically be switched in for one of the DSX-1 cards or to allow interface electronics on the spare card to replace selected ones of the interface electronics on various different DSX-1 cards simultaneously. A pair of controller cards, a primary card and a secondary card, perform the M1-3 multiplexing and demultiplexing and the DS-3 framing and transceiving. The controller cards can be selected or deselected by distributed logic in a sufficiently short time period so that alarms are not set off and so that the transition is hitless. This is accomplished by electronically enabling and disabling the transceiver.