Abstract: A security network provides reduced power consumption and more robust communication of messages in comparison to conventional wireless systems. Reducing power consumption as discussed herein ensures that the security system is able to operate for a long duration of time, potentially with minimal or no power from an electrical grid. Additionally, redundant communication paths as discussed herein provide a more robust way of selectively forwarding security data to a remote server. The availability of multiple communication paths ensures that a respective remote target recipient such as a server resource or remote communication device operated by a user can be notified of a trigger event during power failure conditions, such as when certain communication functionality of a security system is disabled.

Abstract: A programmably sliceable switch-fabric unit (PSSU) and methods of use are disclosed. An N×N? switch matrix is programmably made to operate as if it were a plurality of S×S? virtual switch slices, where S<N and S?<N?. Ingressing requests each specify an egress path (unicast mode) or plural egress paths (multicast mode) in terms of one or more relative egress port numbers. A request translator converts relative egress port numbers into absolute egress port numbers by determining what virtual slice each request belongs to. The translated egress requests are handed off to an arbitration and/or scheduling mechanism for further processing. If the translated request is granted, the corresponding payload egresses through the actual egress port(s) which the translated request asked for.

Abstract: A system and method in accordance with the invention produces an ECC code that is transmitted in the y-bit domain along with data is converted from a native x-bit domain to the y-bit domain. Such a system and method provides a representation of an ECC code that is part of a transmitted serial stream that allows clock recovery and that can use parity checking or other method to verity the integrity of the transmitted ECC code itself.

Abstract: In a system having independently-clocked job-performing circuits (e.g., payload processors) and independently-clocked job-ordering circuits (e.g., request and payload suppliers), coordinating mechanisms are provided for coordinating exchanges between the independently-clocked circuits. The coordinating mechanisms include those that use transmitted time-stamps for scheduling contention-free performances within the job-performing circuits of requested jobs. The coordinating mechanisms additionally or alternatively include static and dynamic rate constraining means that are configured to prevent a faster-clocked one of the independently-clocked circuits from overwhelming a more slowly-clocked other of the independently-clocked circuits. In one implementation, independently-clocked telecommunication-shelves house a distributed set of line cards and switch cards.

Abstract: A programmably sliceable switch-fabric unit (PSSU) and methods of use are disclosed. An N×N? switch matrix is programmably made to operate as if it were a plurality of S×S? virtual switch slices, where S<N and S?<N?. Ingressing requests each specify an egress path (unicast mode) or plural egress paths (multicast mode) in terms of one or more relative egress port numbers. A request translator converts relative egress port numbers into absolute egress port numbers by determining what virtual slice each request belongs to. The translated egress requests are handed off to an arbitration and/or scheduling mechanism for further processing. If the translated request is granted, the corresponding payload egresses through the actual egress port(s) which the translated request asked for.

Abstract: In a system having independently-clocked job-performing circuits (e.g., payload processors) and independently-clocked job-ordering circuits (e.g., request and payload suppliers), coordinating mechanisms are provided for coordinating exchanges between the independently-clocked circuits. The coordinating mechanisms include those that use transmitted time-stamps for scheduling contention-free performances within the job-performing circuits of requested jobs. The coordinating mechanisms additionally or alternatively include static and dynamic rate constraining means that are configured to prevent a faster-clocked one of the independently-clocked circuits from overwhelming a more slowly-clocked other of the independently-clocked circuits. In one implementation, independently-clocked telecommunication-shelves house a distributed set of line cards and switch cards.

Abstract: A digital switching system comprises: (a) a line card layer containing a plurality of real or virtual line cards; (b) a switch card layer containing a plurality of real or virtual switch cards; and (c) an interface layer interposed between the line card layer and the switch card layer for providing serialization support services so that one or more of the line cards and switch cards can be operatively and conveniently disposed in a first shelf or on a first backplane that is spaced apart from a second shelf or from a second backplane supporting others of the line cards and/or switch cards. Such an arrangement allows for scalable expansion of the switching system in terms of number of lines served and/or transmission rates served. The flexibility of the system is owed in part to payload data being carried within payload-carrying regions of so-called ZCell signals as the payload data moves between the line card layer and the switch fabric layer.

Abstract: A method and apparatus for scheduling static and dynamic traffic through a switch fabric are described. The method comprises for each switch slice in a distributed switch fabric, scheduling static traffic by reserving time slots for transmission of the static traffic to at least one destination, and scheduling dynamic traffic so as not to be transmitting the dynamic traffic to the at least one destination during the reserved time slots. The apparatus implements the method and comprises a memory storing a schedule of static traffic, shifters storing dynamic traffic scheduling requests, and a grant scheduler.

Abstract: An apparatus and method for reordering sequence indicated information units into proper sequence are described. The apparatus includes a double-back shifter receiving sequence indicated information units, and at least one circuit coupled to the double-back shifter to repetitively compare, reorder and shift the sequence indicated information units so as to be in proper sequence when shifted out of the double-back shifter. The method includes repetitively comparing, reordering and shifting sequence indicated information units in a double-back shifter so as to be in proper sequence when shifted out of the double-back shifter.

Abstract: A system and method in accordance with the invention produces an ECC code that is transmitted in they-bit domain along with data is converted from a native x-bit domain to they-bit domain. Such a system and method provides a representation of an ECC code that is part of a transmitted serial stream that allows clock recovery and that can use parity checking or other method to verity he integrity of the transmitted ECC code itself.

Abstract: A system and method in accordance with the invention produces an ECC code that is transmitted in the y-bit domain along with data that is converted from a native x-bit domain to the y-bit domain. Such a system and method provides a representation of an ECC code that is part of a transmitted serial stream that allows clock recovery and that can use parity checking or other method to verify the integrity of the transmitted ECC code itself.

Abstract: An apparatus and method for reordering sequence indicated information units into proper sequence are described. The apparatus includes a double-back shifter receiving sequence indicated information units, and at least one circuit coupled to the double-back shifter to repetitively compare, reorder and shift the sequence indicated information units so as to be in proper sequence when shifted out of the double-back shifter. The method includes repetitively comparing, reordering and shifting sequence indicated information units in a double-back shifter so as to be in proper sequence when shifted out of the double-back shifter.

Abstract: A method and apparatus for scheduling static and dynamic traffic through a switch fabric are described. The method comprises for each switch slice in a distributed switch fabric, scheduling static traffic by reserving time slots for transmission of the static traffic to at least one destination, and scheduling dynamic traffic so as not to be transmitting the dynamic traffic to the at least one destination during the reserved time slots. The apparatus implements the method and comprises a memory storing a schedule of static traffic, shifters storing dynamic traffic scheduling requests, and a grant scheduler.

Abstract: A write buffer unit operates in a cached memory microprocessor system by dynamically reconfigurable timed flushing of a queue of coalescing write buffers in the unit. Each time an additional one of the coalescing write buffers is allocated, a time-out period is generated which is inversely related to the number of allocated write buffers. After one of the allocated write buffers times out by exceeding the time-out period with no write activity to the coalescing write buffer, a controller in the unit determines the least recently written to allocated write buffer, and generates control signals to flush that write buffer.

Abstract: A technique and system for reading instruction data from a cache memory with minimum delays. Addresses are calculated and applied to the cache memory in two or more cycles by a pipelined address generation circuit. While data at one address is being retrieved, the next address is being calculated. It is presumed, when calculating the next address, that the current address will return all the data it is addressing. In response to a miss signal received from the cache when no data at the current address is in the cache, the missed data is read from a main system memory and accessed with improved speed. In a system where the cache memory and processor operate at a higher clock frequency than the main system memory, new data is obtained from the main memory during only periodically occurring cache clock cycles. A missed cache memory address is regenerated in a manner to access such new data during the same cache clock cycle that it first becomes available from the main memory.