Abstract: A system for anti-lock brake and traction control has a control circuit comprising a microprocessor on a silicon die. Inputs from several variable reluctance wheel speed sensors are multiplexed to a single channel on the same die for signal processing including diagnostics, A/D conversion, square wave generation for each sensor by a state machine, end wheel speed determination from the square waves. The state machine algorithm tracks signal peaks and valleys and uses a dual hysteresis method of generating output transitions to capture all cycles of a signal having single cycle anomalies while rejecting noise. A single rear wheel sensor having twice the frequency of front wheel sensors for equal wheel speeds is processed twice as often as each front sensor. The diagnostics include detecting sensor and harness short and open circuits by comparison of signals to programmable thresholds and fault timing and latching by gauging open and short signals against programmable time limits.

Abstract: A system for anti-lock brake and traction control has a control circuit comprising a microprocessor on a silicon die. Inputs from several variable reluctance wheel speed sensors are multiplexed to a single channel on the same die for signal processing including diagnostics, A/D conversion, square wave generation for each sensor by a state machine, and wheel speed determination from the square waves. The state machine algorithm tracks signal peaks and valleys and uses a dual hysteresis method of generating output transitions to capture all cycles of a signal having single cycle anomalies while rejecting noise. A single rear wheel sensor having twice the frequency of front wheel sensors for equal wheel speeds is processed twice as often as each front sensor. The diagnostics include detecting sensor and harness short and open circuits by comparison of signals to programmable thresholds and fault timing and latching by gauging open and short signals against programmable time limits.

Abstract: A system for anti-lock brake and traction control has a controller circuit comprising a microprocessor on a silicon die. Inputs from several variable reluctance wheel speed sensors are multiplexed to a single channel on the same die for signal processing including diagnostics, A/D conversion, square wave generation for each sensor by a state machine, and wheel speed determination from the square waves. The diagnostics include detecting sensor and harness short and open circuits by comparison of signals to programmable thresholds and fault timing and latching by gauging open and short signals against programmable time limits. Common mode noise rejection is accomplished by detecting common mode aberration and disabling an A/D converter during the aberrations.

Abstract: An interface circuit is described for interfacing a peripheral device and a microprocessor to enable data transference between a memory location within the peripheral device and a data bus of the microprocessor. In accordance with the type of bus control used by the microprocessor, the interface circuit is operated in either a synchronous mode or an asynchronous mode. The interface includes a state machine that responds to the mode of interface operation, a clock signal provided by the microprocessor, requests from the microprocessor to access an addressed peripheral memory location, and a busy signal from the peripheral device indicating when the peripheral is engaged in transferring data between the interface circuit and an addressed peripheral memory location. Preferably, the interface also operates to detect error conditions based on changes in the access request during data transference between the microprocessor and the peripheral device.

Abstract: A microprocessor is configured as two virtual processors having separate program counters, a common memory and a common execution unit. The processors are configured in a two stage pipeline arrangement and the instructions are interleaved so that as one processor fetches instructions the other executes. One processor runs a fixed length loop of single instructions to provide service of input/output pins at regular and frequent times to afford high resolution. The other processor runs multiple instruction routines. The instructions of either processor can modify the instructions of the other and determine whether a given instruction should be executed. The microprocesor is used as a coprocessor to relieve a main microprocessor of the burdens of managing I/O pins and of running some complex algorithms.

Abstract: A microprocessor is configured as two virtual processors having separate program counters, a common memory and a common execution unit. The processors are configured in a two stage pipeline arrangement and the instructions are interleaved so that as one processor fetches instructions the other executes. One processor runs a fixed length loop of single instructions to provide service of input/output pins at regular and frequency times to afford high resolution. The other processor runs multiple instruction routines. The instructions of either processor can modify the instructions of the other and determine whether a given instruction should be executed. The microprocessor is used as a coprocessor to relieve a main microprocessor of the burdens of managing I/O pins and of running some complex algorithms.